Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 30; no. 3; pp. 388 - 401
• Main Authors: Lerong Cheng, Gupta, P, Spanos, C J, Kun Qian, Lei He
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2011; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceptability; Analytical models; Computer aided design; Correlation; Design engineering; Error analysis; Leakage; Leakage analysis; Mathematical analysis; Mathematical model; Origins; Random variables; Semiconductor device modeling; spatial correlation; SSTA; Systematics; Time measurements; Timing; timing analysis; yield modeling
• DOI: 10.1109/TCAD.2010.2089568
• ISSN: 0278-0070

Modeling spatial variation is important for statistical analysis. Most existing works model spatial variation as spatially correlated random variables. We discuss process origins of spatial variability, all of which indicate that spatial variation comes from deterministic across-wafer variation, and purely random spatial variation is not significant. We analytically study the impact of across-wafer variation and show how it gives an appearance of correlation. We have developed a new die-level variation model considering deterministic across-wafer variation and derived the range of conditions under which ignoring spatial variation altogether may be acceptable. Experimental results show that for statistical timing and leakage analysis, our model is within 2% and 5% error from exact simulation result, respectively, while the error of the existing distance-based spatial variation model is up to 6.5% and 17%, respectively. Moreover, our new model is also faster than the spatial variation model for statistical timing analysis and faster for statistical leakage analysis.