Surface-Roughness-Induced Variability in Nanowire InAs Tunnel FETs

• Published in: IEEE electron device letters Vol. 33; no. 6; pp. 806 - 808
• Main Authors: Conzatti, F., Pala, M. G., Esseni, D.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.06.2012; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Cross-disciplinary physics: materials science; rheology; Devices; Electronics; Exact sciences and technology; Indium arsenides; Materials science; MOSFETs; Nanocomposites; Nanomaterials; Nanoscale materials and structures: fabrication and characterization; Nanostructure; Nanowires; Physics; Quantum wires; Rough surfaces; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Strontium; Surface roughness; Three dimensional; Transistors; tunnel-FET; Tunneling; Tunnels (transportation); variability; MOS technology; MOSFET; Band bending; Tunnel effect; Roughness; Subband; variability; Green function; tunnel-FET; surface roughness; Field effect transistor; Low voltage; Nanowire device; Non equilibrium conditions; Silicon; Nanowires; Comparative study
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2012.2192091

We present a comparative study of the surfaceroughness (SR)-induced variability at low supply voltage V DD = 0.3 V in nanowire InAs tunnel FETs and strained-silicon (sSi) MOSFETs. By exploiting a 3-D full-quantum approach based on the Non-Equilibrium Green's Function formalism, we show that the I on variability in InAs tunnel FETs is much smaller than the I off variability, whereas for V DD = 0.3 V, the sSi MOSFETs working in the subthreshold regime present similar I on and I off variability. We explain the smaller Ion compared with Ioff variability of InAs tunnel FETs by noting that in the source depletion region, where tunneling mainly occurs for V GS = V DD , microscopic subband fluctuations induced by SR are small compared to macroscopic band bending due to the built-in potential of the source junction and to the gate bias. This results in SR-induced variability that is larger in InAs tunnel FETs than in sSi MOSFETs.