Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics

• Published in: IEEE transactions on computers Vol. 59; no. 9; pp. 1250 - 1263
• Main Authors: Guilley, Sylvain, Sauvage, Laurent, Flament, Florent, Vinh-Nga Vong, Hoogvorst, Philippe, Pacalet, Renaud
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE); Institute of Electrical and Electronics Engineers
• Subjects: AES SubBytes; Algorithms; attacks on DPL; backend-level protections; Classification; Computer architecture; Computer information security; Computer Science; Computer simulation; Countermeasures; cryptography; Cryptography and Security; dual-rail with precharge logics (DPL); Electronics; Embedded Systems; Engineering Sciences; Hardware Architecture; implementation-level security; leakage metrics; Libraries; Logic; Logic gates; Mathematical models; Microprocessors; Military technology; Modeling and Simulation; Registers; Routing; Security; side-channel analysis; Studies; Very large scale integration; dual-rail with precharge logics (DPL); AES SubBytes; attacks on DPL; side-channel analysis; backend-level protections; leakage metrics; cryptography; implementation-level security

Cryptographic circuits are nowadays subject to attacks that no longer focus on the algorithm but rather on its physical implementation. Attacks exploiting information leaked by the hardware implementation are called side-channel attacks (SCAs). Among these attacks, the differential power analysis (D...