Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics - Guilley, Sylvain; Sauvage, Laurent; Flament, Florent; Vinh-Nga Vong; Hoogvorst, Philippe; Pacalet, Renaud (IEEE transactions on computers, 2010)
Keywords: AES SubBytes; Algorithms; attacks on DPL; backend-level protections; Classification; Computer architecture; Computer information security; Computer Science; Computer simulation; Countermeasures; cryptography; Cryptography and Security; dual-rail with precharge logics (DPL); Electronics; Embedded Systems; Engineering Sciences; Hardware Architecture; implementation-level security; leakage metrics; Libraries; Logic; Logic gates; Mathematical models; Microprocessors; Military technology; Modeling and Simulation; Registers; Routing; Security; side-channel analysis; Studies; Very large scale integration; dual-rail with precharge logics (DPL); AES SubBytes; attacks on DPL; side-channel analysis; backend-level protections; leakage metrics; cryptography; implementation-level security