Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics

• Published in: IEEE transactions on computers Vol. 59; no. 9; pp. 1250 - 1263
• Main Authors: Guilley, Sylvain, Sauvage, Laurent, Flament, Florent, Vinh-Nga Vong, Hoogvorst, Philippe, Pacalet, Renaud
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE); Institute of Electrical and Electronics Engineers
• Subjects: AES SubBytes; Algorithms; attacks on DPL; backend-level protections; Classification; Computer architecture; Computer information security; Computer Science; Computer simulation; Countermeasures; cryptography; Cryptography and Security; dual-rail with precharge logics (DPL); Electronics; Embedded Systems; Engineering Sciences; Hardware Architecture; implementation-level security; leakage metrics; Libraries; Logic; Logic gates; Mathematical models; Microprocessors; Military technology; Modeling and Simulation; Registers; Routing; Security; side-channel analysis; Studies; Very large scale integration; dual-rail with precharge logics (DPL); AES SubBytes; attacks on DPL; side-channel analysis; backend-level protections; leakage metrics; cryptography; implementation-level security
• DOI: 10.1109/TC.2010.104
• ISSN: 0018-9340

Cryptographic circuits are nowadays subject to attacks that no longer focus on the algorithm but rather on its physical implementation. Attacks exploiting information leaked by the hardware implementation are called side-channel attacks (SCAs). Among these attacks, the differential power analysis (DPA) established by Paul Kocher et al. in 1998 represents a serious threat for CMOS VLSI implementations. Different countermeasures that aim at reducing the information leaked by the power consumption have been published. Some of these countermeasures use sophisticated back-end-level constraints to increase their strength. As suggested by some preliminary works (e.g., by Li from Cambridge University), the prediction of the actual security level of such countermeasures remains an open research area. This paper tackles this issue on the example of the AES SubBytes primitive. Thirteen implementations of SubBytes, in unprotected, WDDL, and SecLib logic styles with various back-end-level arrangements are studied. Based on simulation and experimental results, we observe that static evaluations on extracted netlists are not relevant to classify variants of a countermeasure. Instead, we conclude that the fine-grained timing behavior is the main reason for security weaknesses. In this respect, we prove that SecLib, immune to early-evaluation problems, is much more resistant against DPA than WDDL.