Guilley, S., Sauvage, L., Flament, F., Vong, V., Hoogvorst, P., & Pacalet, R. (2010). Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics. IEEE transactions on computers, 59(9), 1250-1263. https://doi.org/10.1109/TC.2010.104
Chicago Style (17th ed.) CitationGuilley, Sylvain, Laurent Sauvage, Florent Flament, Vinh-Nga Vong, Philippe Hoogvorst, and Renaud Pacalet. "Evaluation of Power Constant Dual-Rail Logics Countermeasures Against DPA with Design Time Security Metrics." IEEE Transactions on Computers 59, no. 9 (2010): 1250-1263. https://doi.org/10.1109/TC.2010.104.
MLA (9th ed.) CitationGuilley, Sylvain, et al. "Evaluation of Power Constant Dual-Rail Logics Countermeasures Against DPA with Design Time Security Metrics." IEEE Transactions on Computers, vol. 59, no. 9, 2010, pp. 1250-1263, https://doi.org/10.1109/TC.2010.104.