Approximation scheme for restricted discrete gate sizing targeting delay minimization

• Published in: Journal of combinatorial optimization Vol. 21; no. 4; pp. 497 - 510
• Main Authors: Liao, Chen, Hu, Shiyan
• Format: Journal Article
• Language: English
• Published: Boston Springer US 01.05.2011; Springer
• Subjects: Applied sciences; Combinatorics; Convex and Discrete Geometry; Electronics; Exact sciences and technology; Flows in networks. Combinatorial problems; Integrated circuits; Integrated circuits by function (including memories and processors); Mathematical Modeling and Industrial Mathematics; Mathematical programming; Mathematics; Mathematics and Statistics; Operational research and scientific management; Operational research. Management science; Operations Research/Decision Theory; Optimization; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Theory of Computation; Fully polynomial time approximation scheme; VLSI design; Combinatorial optimization; Delay optimization; Discrete gate sizing; Costs; VLSI circuit; Targeting; Circuit design; Query; Polynomial approximation; Minimization; Logic gate; Approximation algorithm; Modeling; Delay; Polynomial time; Delay circuit; Dimensioning; Heuristic method; Discrete time; Dynamic programming; Oracle; Computer aided design

Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such that the delay of a combinational circuit is minimized while the cost constraint is satisfied. It is one of the most studi...