The effect of remnant CdSe layers on the performance of CdSeTe/CdTe photovoltaic devices - Liu, Xiaolei; Abbas, Ali; Togay, Mustafa; Kornienko, Vlad; Greenhalgh, Rachael; Curson, Kieran; Bowers, Jake; Barth, Kurt; Walls, Michael; Bastola, Ebin; Barros-King, Griffin; Phillips, Adam B.; et al. (Solar energy materials and solar cells, 2024)
Thin film CdTe-based photovoltaic devices have achieved high efficiency above 22 %. The recent improvement in efficiency is due to Se alloying in the CdTe absorbers to form a CdSeTe/CdTe structure. The subsequent band gap grading increases the short circuit current density. The Se can be introduced by depositing a precursor thin film of either CdSe or a CdSeTe alloy and then diffusing the Se into the CdTe during the high temperature cadmium chloride activation process. Using CdSe is preferred because it is easier to control the Se concentration. However, during fabrication of the CdSeTe/CdTe devices, the CdSe thickness needs to be precisely controlled to prevent the retention of a CdSe remnant layer after the activation treatment. Retention of a remnant CdSe layer causes a dramatic reduction in device efficiency. In this work, we show that the reduction in efficiency is caused by a number of factors. The remnant CdSe layer is n-type which moves the position of the p-n junction. Also, it is widely thought that the CdSe remnants are photo-inactive. In this work, we clarify that the individual CdSe grains are actually highly photo-active. However, the grain sizes in the CdSe remnant and the adjacent CdSeTe layer are very small resulting in a high grain boundary area. Although the grain boundaries are passivated with chlorine, cathodoluminescence imaging and electrical measurements show that this is only partially effective. Also, EQE measurements show that the remnant CdSe causes parasitic absorption. Overall, the remnant CdSe layer causes a reduction in short circuit current density and device efficiency. The thickness of the CdSe precursor layer and the cadmium chloride activation process conditions must be precisely optimised to ensure that all the CdSe is consumed and inter-diffused to form the CdSeTe alloy for highest efficiency devices. •The retention of a remnant CdSe layer causes a dramatic reduction in short circuit current and device efficiency.•The small grain size in the CdSe remnant and the adjacent CdSeTe layer greatly reduces short circuit current.•The band gap energy and high photo-activity of CdSe make it promising for silicon-based tandem device applications.