Insight of surface treatments for CMOS compatibility of InAs nanowires

• Published in: Nano research Vol. 12; no. 3; pp. 581 - 586
• Main Authors: Dhungana, Daya S., Hemeryck, Anne, Sartori, Nicolo, Fazzini, Pier-Francesco, Cristiano, Filadelfo, Plissard, Sébastien R.
• Format: Journal Article
• Language: English
• Published: Beijing Tsinghua University Press 01.03.2019; Springer Nature B.V; Springer
• Subjects: Arsenic; Atomic/Molecular Structure and Spectra; Biomedicine; Biotechnology; Chemistry and Materials Science; CMOS; Compatibility; Condensed Matter; Condensed Matter Physics; Degassing; Density functional theory; Epitaxial growth; Epitaxy; Growth conditions; High aspect ratio; Indium arsenides; Materials Science; Metalorganic chemical vapor deposition; Molecular beam epitaxy; Nanotechnology; Nanowires; Physics; Research Article; Substrates; Surface preparation; Vapor phase epitaxy; Vapor phases; Vapors; III-V semiconductors on silicon; density functional theory (DFT) modeling; InAs; nanowires; self-catalyzed growth; growth modeling; hydrogen preparation
• DOI: 10.1007/s12274-018-2257-8
• ISSN: 1998-0124

A CMOS compatible process is presented in order to grow self-catalyzed InAs nanowires on silicon by molecular beam epitaxy. The crucial step of this process is a new in-situ surface preparation under hydrogen (gas or plasma) during the substrate degassing combined with an in-situ arsenic annealing prior to growth. Morphological and structural characterizations of the InAs nanowires are presented and growth mechanisms are discussed in detail. The major influence of surface termination is exposed both experimentally and theoretically using statistics on ensemble of nanowires and density functional theory (DFT) calculations. The differences observed between Molecular Beam Epitaxy (MBE) and Metal Organic Vapor Phase Epitaxy (MOVPE) growth of InAs nanowires can be explained by these different surfaces terminations. The transition between a vapor solid (VS) and a vapor liquid solid (VLS) growth mechanism is presented. Optimized growth conditions lead to very high aspect ratio nanowires (up to 50 nm in diameter and 3 micron in length) without passing the 410 °C thermal limit, which makes the whole process CMOS compatible. Overall, our results suggest a new method for surface preparation and a possible tuning of the growth mechanism using different surface terminations.