Air-gap formation during IMD deposition to lower interconnect capacitance

The use of air-gaps between interconnect metal lines to reduce interconnect capacitance has been explored. Simulations were performed to determine the reduction in capacitance obtainable using air-gaps. The formation of air-gaps in the isolation oxide between metal lines was simulated using Stanford...

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Bibliographic Details
Published inIEEE electron device letters Vol. 19; no. 1; pp. 16 - 18
Main Authors Shieh, B., Saraswat, K.C., McVittie, J.P., List, S., Nag, S., Islamraja, M., Havemann, R.H.
Format Journal Article
LanguageEnglish
Published IEEE 01.01.1998
Subjects
Air gaps
Capacitance
Conducting materials
Delay
Dielectric materials
Etching
Geometry
Solid modeling
Thermal conductivity
Thermal stability
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Summary:The use of air-gaps between interconnect metal lines to reduce interconnect capacitance has been explored. Simulations were performed to determine the reduction in capacitance obtainable using air-gaps. The formation of air-gaps in the isolation oxide between metal lines was simulated using Stanford Profile Emulator for Etching and Deposition in IC Engineering (SPEEDIE). The capacitance of the SPEEDIE profiles was then extracted using Raphael (an electrical analysis simulator from TMA). The feasibility of air-gaps was also demonstrated experimentally. Fabricated air-gap structures exhibited a 40% reduction in capacitance when compared to a HDP-CVD oxide gap-fill process with K=4.1. Additionally, the air-gap structures did not exhibit any appreciable leakage current.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
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content type line 23
ISSN:0741-3106
1558-0563
DOI:10.1109/55.650339