Exploiting parallelism in geometry processing with general purpose processors and floating-point SIMD instructions

• Published in: IEEE transactions on computers Vol. 49; no. 9; pp. 934 - 946
• Main Authors: Chia-Lin Yang, Sano, B., Lebeck, A.R.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2000; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 3-D graphics; Application software; Computational geometry; Computer graphics; Cycle time; Dynamic scheduling; Floating point arithmetic; Geometry; Hardware; Microarchitecture; Parallel processing; Performance enhancement; Processor scheduling; Processors; Reduced instruction set computing; Rendering; Rendering (computer graphics); Tasks; Three dimensional
• DOI: 10.1109/12.869324
• ISSN: 0018-9340

Three-dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geometry processing of 3D graphics on the host CPU and have specialized hardware handle the rendering task. In this paper, we analyze microarchitecture and SIMD instruction set enhancements to a RISC superscalar processor for exploiting parallelism in geometry processing for 3D computer graphics. Our results show that 3D geometry processing has inherent parallelism. Adding SIMD operations improves performance from 8 percent to 28 percent on a 4-issue dynamically scheduled processor that can issue at most two floating-point operations. In comparison, an 8-issue processor, ignoring cycle time effects, can achieve 20 to 60 percent performance improvement over a 4-issue. If processor cycle time scales with the number of ports to the register file, then doubling only the floating-point issue width of a 4-issue processor with SIMD instructions gives the best performance among the architectural configurations that we examine (the most aggressive configuration is an 8-issue processor with SIMD instructions).