Scalable Microring-Based Silicon Clos Switch Fabric With Switch-and-Select Stages

• Published in: IEEE journal of selected topics in quantum electronics Vol. 25; no. 5; pp. 1 - 11
• Main Authors: Qixiang Cheng, Bahadori, Meisam, Yu-Han Hung, Yishen Huang, Abrams, Nathan, Bergman, Keren
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE); Institute of Electrical and Electronics Engineers
• Subjects: Blocking; Crosstalk; Fabrics; Insertion loss; microring resonators; Network switching; Optical switches; Parameters; photonic integrated circuits; Photonics; Silicon; silicon photonics; switch architectures; Switching; Topology
• ISSN: 1077-260X; 1558-4542
• DOI: 10.1109/JSTQE.2019.2911421

We propose and analyze a scalable microring-based Clos switch fabric architecture constructed with switch-and-select switching stages. A silicon 4 × 4 building block that was designed and fabricated through American Institute for Manufacturing Integrated Photonics is used for the proof-of-principle demonstration of a 16 × 16 Clos switch fabric. By fully blocking the first-order crosstalk, the 4 × 4 device is measured to show a crosstalk ratio in the range of -57 to -48.5 dB, enabling better than -39 dB crosstalk for the 16 × 16 switch. Our study shows that the three-stage Clos design enables up to a factor of 4 in the reduction of the number of switching cells compared to single-stage switch-and-select fabrics. We further explore the design space for both first-order and second-order switching elements using the foundry-validated parameters and how these factors impact the performance and scalability of the three-stage Clos switch. A detailed power penalty map is drawn for Clos switch fabrics with various scales, which reveals that the ultimate key limiting factor is the shuffle insertion loss. An optimized 32-port Clos switch fabric using foundry-enabled parameters is shown to have a less than 10-dB power penalty.