Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic

• Published in: IET circuits, devices & systems Vol. 1; no. 1; pp. 102 - 110
• Main Authors: JABERIPUR, G, PARHAMI, B
• Format: Journal Article
• Language: English
• Published: Stevenage Institution of Engineering and Technology 01.02.2007; John Wiley & Sons, Inc
• Subjects: Applied sciences; Arithmetic; Circuit properties; Circuits; Constants; Digital circuits; Digits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Encoding; Exact sciences and technology; High speed; Redundant; Representations; Performance evaluation; Arithmetic circuit; Circuit gain; Redundant system; Computer arithmetic; Coding; Algorithm; Time constant
• DOI: 10.1049/iet-cds:20050228
• ISSN: 1751-858X

Redundant representations play an important role in high-speed computer arithmetic. One key reason is that such representations support carry-free addition, that is, addition in a small, constant time, independent of operand widths. The implications of stored-transfer representation of digit sets and the associated addition schemes, as an extension of the stored-carry concept to redundant number systems, on the speed and cost of arithmetic algorithms, are explored. Two's-complement digits as the main part and any two-valued digit in place of a stored carry are allowed, leading to further broadening of the generalised signed-digit representations. The characteristics of the digit sets, possibly not having zero as a member, that allow for most efficient carry-free addition, are investigated. A circuit speed is gained from storing or saving, instead of combining through addition, the interdigit transfers generated during the carry-free addition process. Encoding efficiency is gained from using a twit-transfer set encoded by one logical bit, where more bits would otherwise be needed to represent a transfer value.