Lazy simulation of digital logic

• Published in: Computer aided design Vol. 23; no. 7; pp. 506 - 513
• Main Authors: Charlton, C.C., Jackson, D., Leng, P.H.
• Format: Journal Article
• Language: English
• Published: Oxford Elsevier Ltd 01.09.1991; Elsevier Science
• Subjects: Applied sciences; Circuit properties; digital systems; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; lazy evaluation; simulation; digital systems; lazy evaluation; simulation; Logic circuit; VLSI circuit; Circuit design; Digital circuit; Minimization; Numerical simulation; Computer aided design; Calculating time
• DOI: 10.1016/0010-4485(91)90049-3
• ISSN: 0010-4485

The use of software simulators as a means for developing and validating digital-logic systems has become well established, and the complexity of today's circuits makes the accuracy and efficiency of simulation of prime importance. It is suggested in the paper, however, that conventional simulation techniques are inadequate for this purpose: to represent the inherently parallel activity of a digital circuit in a sequential simulation program, an unnecessary, and often arbitrary, sequence of events is imposed. This is a process that is error-prone and inefficient. In an attempt to reason about the nature of the simulation problem, a model of hardware has been derived that makes use of the principles involved in functional programming; in particular, the concept of lazy evaluation has been adopted as a way of minimizing the amount of simulation activity required. This model has been used as the basis for the generation of several simulators, and the paper presents an analysis of the performance of such a lazy simulator in comparison with those of the more usual simulation mechanisms. The results of this are extremely encouraging.