True Load Balancing for Matricized Tensor Times Khatri-Rao Product

• Published in: IEEE transactions on parallel and distributed systems Vol. 32; no. 8; pp. 1974 - 1986
• Main Authors: Abubaker, Nabil, Acer, Seher, Aykanat, Cevdet
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Computational efficiency; Computational modeling; Computer architecture; Computing costs; CP Decomposition; Distributed memory; Fine-grain hypergraph partitioning; Fragmentation; Load; Load balancing; Load modeling; Mathematical analysis; MATHEMATICS AND COMPUTING; Microprocessors; MTTKRP; Partitioning; Partitioning algorithms; Processors; Program processors; Sparse matrices; Sparse tensors; Tensors
• DOI: 10.1109/TPDS.2021.3053836
• ISSN: 1045-9219

MTTKRP is the bottleneck operation in algorithms used to compute the CP tensor decomposition. For sparse tensors, utilizing the compressed sparse fibers (CSF) storage format and the CSF-oriented MTTKRP algorithms is important for both memory and computational efficiency on distributed-memory architectures. Existing intelligent tensor partitioning models assume the computational cost of MTTKRP to be proportional to the total number of nonzeros in the tensor. However, this is not the case for the CSF-oriented MTTKRP on distributed-memory architectures. We outline two deficiencies of nonzero-based intelligent partitioning models when CSF-oriented MTTKRP operations are performed locally: failure to encode processors' computational loads and increase in total computation due to fiber fragmentation. We focus on existing fine-grain hypergraph model and propose a novel vertex weighting scheme that enables this model encode correct computational loads of processors. We also propose to augment the fine-grain model by fiber nets for reducing the increase in total computational load via minimizing fiber fragmentation. In this way, the proposed model encodes minimizing the load of the bottleneck processor. Parallel experiments with real-world sparse tensors on up to 1024 processors prove the validity of the outlined deficiencies and demonstrate the merit of our proposed improvements in terms of parallel runtimes.