Equidistance routing in high-speed VLSI layout design
In VLSI layout design, certain nets in a given net set are required to propagate their signals within a tolerable skew of delays. Though the delay of the signal on a wire is determined by a complex environment, it is hard to satisfy this requirement unless all the concerned nets are routed within a...
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Published in | Integration (Amsterdam) Vol. 38; no. 3; pp. 439 - 449 |
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Main Authors | , , , |
Format | Journal Article Conference Proceeding |
Language | English |
Published |
Amsterdam
Elsevier B.V
01.01.2005
Elsevier Science |
Subjects | |
Online Access | Get full text |
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