Equidistance routing in high-speed VLSI layout design

• Published in: Integration (Amsterdam) Vol. 38; no. 3; pp. 439 - 449
• Main Authors: Kubo, Yukiko, Miyashita, Hiroshi, Kajitani, Yoji, Tateishi, Kazuyuki
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Amsterdam Elsevier B.V 01.01.2005; Elsevier Science
• Subjects: Applied sciences; Channel routing; Circuit properties; Design. Technologies. Operation analysis. Testing; Dynamic programming; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Equidistance routing; Exact sciences and technology; Integrated circuits; Minimization of total length; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Switch-box routing; Switching, multiplexing, switched capacity circuits; Symmetric-slant grid; Switch-box routing; Channel routing; Dynamic programming; Equidistance routing; Symmetric-slant grid; Minimization of total length; VLSI circuit; Circuit design; Integrated circuit design; Algorithm; Integrated circuit layout; Signal delay; Interconnection; Integrated circuit; Delay time; Selector switch

In VLSI layout design, certain nets in a given net set are required to propagate their signals within a tolerable skew of delays. Though the delay of the signal on a wire is determined by a complex environment, it is hard to satisfy this requirement unless all the concerned nets are routed within a...