Equidistance routing in high-speed VLSI layout design
In VLSI layout design, certain nets in a given net set are required to propagate their signals within a tolerable skew of delays. Though the delay of the signal on a wire is determined by a complex environment, it is hard to satisfy this requirement unless all the concerned nets are routed within a...
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Published in | Integration (Amsterdam) Vol. 38; no. 3; pp. 439 - 449 |
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Main Authors | , , , |
Format | Journal Article Conference Proceeding |
Language | English |
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Amsterdam
Elsevier B.V
01.01.2005
Elsevier Science |
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Abstract | In VLSI layout design, certain nets in a given net set are required to propagate their signals within a tolerable skew of delays. Though the delay of the signal on a wire is determined by a complex environment, it is hard to satisfy this requirement unless all the concerned nets are routed within a certain skew of length. In this paper, we propose L-equidistance routing, which routes the concerned nets with a prescribed length L. After a basic technique of L-equidistance routing of a single 1-sink net, an algorithm is presented for the channel routing of plural multi-sink nets. The key idea is in the symmetric-slant grid interconnect scheme by which the problem is reduced to a grid routing problem. In L-equidistance routing of a channel, the total length of a n-sink net is not unique for n⩾3. An algorithm based on dynamic programming to solve this minimization problem is presented. Then, L-equidistance switch-box routing is discussed based on the L-equidistance channel routing. Algorithms are explained on the Euclidean space. But it is shown that a straightforward transformation of the routes to those on the Manhattan grid is possible keeping the property of equidistance. The proposing channel routing algorithm was implemented and applied to random data to demonstrate their ability. |
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AbstractList | In VLSI layout design, certain nets in a given net set are required to propagate their signals within a tolerable skew of delays. Though the delay of the signal on a wire is determined by a complex environment, it is hard to satisfy this requirement unless all the concerned nets are routed within a certain skew of length. In this paper, we propose L-equidistance routing, which routes the concerned nets with a prescribed length L. After a basic technique of L-equidistance routing of a single 1-sink net, an algorithm is presented for the channel routing of plural multi-sink nets. The key idea is in the symmetric-slant grid interconnect scheme by which the problem is reduced to a grid routing problem. In L-equidistance routing of a channel, the total length of a n-sink net is not unique for n3. An algorithm based on dynamic programming to solve this minimization problem is presented. Then, L-equidistance switch-box routing is discussed based on the L-equidistance channel routing. Algorithms are explained on the Euclidean space. But it is shown that a straightforward transformation of the routes to those on the Manhattan grid is possible keeping the property of equidistance. The proposing channel routing algorithm was implemented and applied to random data to demonstrate their ability. In VLSI layout design, certain nets in a given net set are required to propagate their signals within a tolerable skew of delays. Though the delay of the signal on a wire is determined by a complex environment, it is hard to satisfy this requirement unless all the concerned nets are routed within a certain skew of length. In this paper, we propose L-equidistance routing, which routes the concerned nets with a prescribed length L. After a basic technique of L-equidistance routing of a single 1-sink net, an algorithm is presented for the channel routing of plural multi-sink nets. The key idea is in the symmetric-slant grid interconnect scheme by which the problem is reduced to a grid routing problem. In L-equidistance routing of a channel, the total length of a n-sink net is not unique for n⩾3. An algorithm based on dynamic programming to solve this minimization problem is presented. Then, L-equidistance switch-box routing is discussed based on the L-equidistance channel routing. Algorithms are explained on the Euclidean space. But it is shown that a straightforward transformation of the routes to those on the Manhattan grid is possible keeping the property of equidistance. The proposing channel routing algorithm was implemented and applied to random data to demonstrate their ability. |
Author | Tateishi, Kazuyuki Kajitani, Yoji Miyashita, Hiroshi Kubo, Yukiko |
Author_xml | – sequence: 1 givenname: Yukiko surname: Kubo fullname: Kubo, Yukiko email: kubo@env.kitakyu-u.ac.jp organization: Department of Information and Media Sciences, The University of Kitakyushu, 1–1 Hibikino, Wakamatsu-ku, Kitakyushu, Fukuoka, Japan – sequence: 2 givenname: Hiroshi surname: Miyashita fullname: Miyashita, Hiroshi organization: Department of Information and Media Sciences, The University of Kitakyushu, 1–1 Hibikino, Wakamatsu-ku, Kitakyushu, Fukuoka, Japan – sequence: 3 givenname: Yoji surname: Kajitani fullname: Kajitani, Yoji organization: Department of Information and Media Sciences, The University of Kitakyushu, 1–1 Hibikino, Wakamatsu-ku, Kitakyushu, Fukuoka, Japan – sequence: 4 givenname: Kazuyuki surname: Tateishi fullname: Tateishi, Kazuyuki organization: Cadence Design Systems, Japan, 3–17–6 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa, Japan |
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Keywords | Switch-box routing Channel routing Dynamic programming Equidistance routing Symmetric-slant grid Minimization of total length VLSI circuit Circuit design Integrated circuit design Algorithm Integrated circuit layout Signal delay Interconnection Integrated circuit Delay time Selector switch |
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References | Tsay (bib5) 1991 Kahng, Cong, Robins (bib6) 1993; 12 Deutsch (bib10) 1976 Reed, Vincentelli, Santamauro (bib8) 1985; 4 Chao, Hsu, Ho (bib4) 1992 Yoshimura, Kuh (bib9) 1982; 1 Ozdal, Wong (bib7) 2003 Hu, Spatnekar (bib2) 2000 Huang, Xue, Huang, Cheng, Kuh (bib3) 1997; 16 Cong, Kahng, Robins, Sarrafzadeh, Wong (bib1) 1992; 11 Yoshimura (10.1016/j.vlsi.2004.07.008_bib9) 1982; 1 Huang (10.1016/j.vlsi.2004.07.008_bib3) 1997; 16 Chao (10.1016/j.vlsi.2004.07.008_bib4) 1992 Cong (10.1016/j.vlsi.2004.07.008_bib1) 1992; 11 Kahng (10.1016/j.vlsi.2004.07.008_bib6) 1993; 12 Hu (10.1016/j.vlsi.2004.07.008_bib2) 2000 Tsay (10.1016/j.vlsi.2004.07.008_bib5) 1991 Deutsch (10.1016/j.vlsi.2004.07.008_bib10) 1976 Reed (10.1016/j.vlsi.2004.07.008_bib8) 1985; 4 Ozdal (10.1016/j.vlsi.2004.07.008_bib7) 2003 |
References_xml | – start-page: 330 year: 1991 end-page: 339 ident: bib5 article-title: Exact zero skew publication-title: Proceeding of International Conference on Computer-Aided Design contributor: fullname: Tsay – volume: 12 start-page: 1157 year: 1993 end-page: 1169 ident: bib6 article-title: Matching based models for high performance clock routing publication-title: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. contributor: fullname: Robins – start-page: 425 year: 1976 end-page: 433 ident: bib10 article-title: A dogleg channel router publication-title: Proceeding of Design Automation Conference contributor: fullname: Deutsch – start-page: 518 year: 1992 end-page: 523 ident: bib4 article-title: Zero skew clock net routing publication-title: Proceeding of Design Automation Conference contributor: fullname: Ho – volume: 1 start-page: 25 year: 1982 end-page: 30 ident: bib9 article-title: Efficient algorithms for channel routing publication-title: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. contributor: fullname: Kuh – start-page: 394 year: 2003 end-page: 400 ident: bib7 article-title: Length-matching routing for high-speed printed circuit boards publication-title: Proceeding of International Conference on Computer-Aided Design contributor: fullname: Wong – start-page: 99 year: 2000 end-page: 103 ident: bib2 article-title: A timing-constrained algorithm for simultaneous global routing of multiple nets publication-title: Proceeding of International Conference on Computer-Aided Design contributor: fullname: Spatnekar – volume: 16 start-page: 1323 year: 1997 end-page: 1330 ident: bib3 article-title: TIGER publication-title: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. contributor: fullname: Kuh – volume: 11 start-page: 739 year: 1992 end-page: 752 ident: bib1 article-title: Provably good performance-driven global routing publication-title: IEEE Trans. Comput. Aided Des. of Integr. Circuits Syst. contributor: fullname: Wong – volume: 4 start-page: 208 year: 1985 end-page: 219 ident: bib8 article-title: A new symbolic channel router publication-title: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. contributor: fullname: Santamauro – volume: 11 start-page: 739 issue: 6 year: 1992 ident: 10.1016/j.vlsi.2004.07.008_bib1 article-title: Provably good performance-driven global routing publication-title: IEEE Trans. Comput. Aided Des. of Integr. Circuits Syst. doi: 10.1109/43.137519 contributor: fullname: Cong – start-page: 394 year: 2003 ident: 10.1016/j.vlsi.2004.07.008_bib7 article-title: Length-matching routing for high-speed printed circuit boards contributor: fullname: Ozdal – start-page: 99 year: 2000 ident: 10.1016/j.vlsi.2004.07.008_bib2 article-title: A timing-constrained algorithm for simultaneous global routing of multiple nets contributor: fullname: Hu – start-page: 330 year: 1991 ident: 10.1016/j.vlsi.2004.07.008_bib5 article-title: Exact zero skew contributor: fullname: Tsay – volume: 4 start-page: 208 issue: 3 year: 1985 ident: 10.1016/j.vlsi.2004.07.008_bib8 article-title: A new symbolic channel router publication-title: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. doi: 10.1109/TCAD.1985.1270117 contributor: fullname: Reed – volume: 1 start-page: 25 issue: 1 year: 1982 ident: 10.1016/j.vlsi.2004.07.008_bib9 article-title: Efficient algorithms for channel routing publication-title: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. doi: 10.1109/TCAD.1982.1269993 contributor: fullname: Yoshimura – start-page: 425 year: 1976 ident: 10.1016/j.vlsi.2004.07.008_bib10 article-title: A dogleg channel router contributor: fullname: Deutsch – start-page: 518 year: 1992 ident: 10.1016/j.vlsi.2004.07.008_bib4 article-title: Zero skew clock net routing contributor: fullname: Chao – volume: 16 start-page: 1323 issue: 11 year: 1997 ident: 10.1016/j.vlsi.2004.07.008_bib3 article-title: TIGER publication-title: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. doi: 10.1109/43.663822 contributor: fullname: Huang – volume: 12 start-page: 1157 issue: 8 year: 1993 ident: 10.1016/j.vlsi.2004.07.008_bib6 article-title: Matching based models for high performance clock routing publication-title: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. doi: 10.1109/43.238608 contributor: fullname: Kahng |
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Snippet | In VLSI layout design, certain nets in a given net set are required to propagate their signals within a tolerable skew of delays. Though the delay of the... |
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SubjectTerms | Applied sciences Channel routing Circuit properties Design. Technologies. Operation analysis. Testing Dynamic programming Electric, optical and optoelectronic circuits Electronic circuits Electronics Equidistance routing Exact sciences and technology Integrated circuits Minimization of total length Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Switch-box routing Switching, multiplexing, switched capacity circuits Symmetric-slant grid |
Title | Equidistance routing in high-speed VLSI layout design |
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