Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer
We combined a "via-last through-silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer" with the solder bonding process using Ar fast atom beam (FAB), and realized the fabrication and three-dimensional (3D) stacking of a high-density TSV arra...
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Published in | Japanese Journal of Applied Physics Vol. 58; no. SD; p. SDDL09 |
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Main Authors | , , , , , , |
Format | Journal Article |
Language | English |
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Tokyo
IOP Publishing
01.06.2019
Japanese Journal of Applied Physics |
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Abstract | We combined a "via-last through-silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer" with the solder bonding process using Ar fast atom beam (FAB), and realized the fabrication and three-dimensional (3D) stacking of a high-density TSV array chip. The size of the TSV array was 76 × 500. The diameter and length of the TSV were 6 and 21-22 m, respectively. As the TSV array chip was very thin (approximately 26 m) and had a strip-like shape, it was fragile and warped by approximately 90 m. Hence, an electrostatic chuck was introduced and the TSV array chip was stacked by using a soft material (Cu-Ni-Sn based solder) as a bump and performing low-pressing-load low-temperature bonding with Ar FAB. As a result, the warpage of TSV array chip was suppressed and the TSV array chip was stacked without causing damage to the TSV and Si region. In addition, it was confirmed that the (i) leakage current between TSV-bump pairs is small, (ii) multilayer wiring + TSV + bump connection exhibit low resistance, and (iii) daisy chain is perfectly connected to up to 38 000 TSVs. These results are due to the effects of notchless Si etching, wet cleaning of the first metal layer, introduction of an electrostatic chuck, low-pressing-load low-temperature bonding with a soft material, and Ar FAB. This process will facilitate the development of face-up type 3D stacked sensor systems. |
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AbstractList | We combined a "via-last through-silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer" with the solder bonding process using Ar fast atom beam (FAB), and realized the fabrication and three-dimensional (3D) stacking of a high-density TSV array chip. The size of the TSV array was 76 × 500. The diameter and length of the TSV were 6 and 21-22 m, respectively. As the TSV array chip was very thin (approximately 26 m) and had a strip-like shape, it was fragile and warped by approximately 90 m. Hence, an electrostatic chuck was introduced and the TSV array chip was stacked by using a soft material (Cu-Ni-Sn based solder) as a bump and performing low-pressing-load low-temperature bonding with Ar FAB. As a result, the warpage of TSV array chip was suppressed and the TSV array chip was stacked without causing damage to the TSV and Si region. In addition, it was confirmed that the (i) leakage current between TSV-bump pairs is small, (ii) multilayer wiring + TSV + bump connection exhibit low resistance, and (iii) daisy chain is perfectly connected to up to 38 000 TSVs. These results are due to the effects of notchless Si etching, wet cleaning of the first metal layer, introduction of an electrostatic chuck, low-pressing-load low-temperature bonding with a soft material, and Ar FAB. This process will facilitate the development of face-up type 3D stacked sensor systems. We combined a "via-last through-silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer" with the solder bonding process using Ar fast atom beam (FAB), and realized the fabrication and three-dimensional (3D) stacking of a high-density TSV array chip. The size of the TSV array was 76 × 500. The diameter and length of the TSV were 6 and 21–22 μm, respectively. As the TSV array chip was very thin (approximately 26 μm) and had a strip-like shape, it was fragile and warped by approximately 90 μm. Hence, an electrostatic chuck was introduced and the TSV array chip was stacked by using a soft material (Cu–Ni–Sn based solder) as a bump and performing low-pressing-load low-temperature bonding with Ar FAB. As a result, the warpage of TSV array chip was suppressed and the TSV array chip was stacked without causing damage to the TSV and Si region. In addition, it was confirmed that the (i) leakage current between TSV-bump pairs is small, (ii) multilayer wiring + TSV + bump connection exhibit low resistance, and (iii) daisy chain is perfectly connected to up to 38 000 TSVs. These results are due to the effects of notchless Si etching, wet cleaning of the first metal layer, introduction of an electrostatic chuck, low-pressing-load low-temperature bonding with a soft material, and Ar FAB. This process will facilitate the development of face-up type 3D stacked sensor systems. |
Author | Watanabe, Naoya Nakamura, Akio Yanagisawa, Azusa Kikuchi, Hidekazu Shimamoto, Haruo Aoyagi, Masahiro Kikuchi, Katsuya |
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References | Watanabe N. (17) 2017; 56 24 25 Lärmer F. (23) 1992 Kessel C. R. (20) Sukegawa S. (4) Watanabe N. (15) Sugiya T. (21) 2012 Tsugawa H. (6) 11 Wang Y. H. (18) Cho B. H. (26) 2007; 46 14 Wei F. (22) Kim D. H. (7) 19 Kang U. (10) Koyanagi M. (1) Higashi K. (12) 2 Ramaswami S. (27) 2008 Haruta T. (5) 8 9 Watanabe N. (3) 2010; 49 Watanabe N. (16) Santarini M. (13) 2011; 4 |
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Snippet | We combined a "via-last through-silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer" with the solder bonding... |
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SubjectTerms | Arrays Bonding Cleaning Copper Dry cleaners Etching Integrated circuits Interconnections Leakage current Low resistance Multilayers Nickel Pressing Silicon Stacking Tin Warpage Wiring |
Title | Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer |
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