A CNN Accelerator on FPGA Using Depthwise Separable Convolution

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 65; no. 10; pp. 1415 - 1419
• Main Authors: Bai, Lin, Zhao, Yiming, Huang, Xinming
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Artificial neural networks; Bandwidth; Computation; Computer vision; Convolution; Convolutional neural network; Engines; Field programmable gate arrays; FPGA; Frames per second; hardware accelerator; MobileNetV2; Model accuracy; Neural networks; Pattern recognition; Portable equipment; System-on-chip

Convolutional neural networks (CNNs) have been widely deployed in the fields of computer vision and pattern recognition because of their high accuracy. However, large convolution operations are computing intensive and often require a powerful computing platform such as a graphics processing unit. Th...