ECO Timing Optimization Using Spare Cells and Technology Remapping

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 29; no. 5; pp. 697 - 710
• Main Authors: Ho, Kuan-Hsien, Chen, Yen-Pin, Fang, Jia-Wei, Chang, Yao-Wen
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Computer bugs; Cost function; Design engineering; Design optimization; Dynamic programming; Dynamics; Engineering change order (ECO); gate sizing; Heuristic algorithms; Integrated circuit technology; Optimization; physical design; Rewiring; Space technology; spare cells; Studies; technology remapping; Time measurements; Time to market; Timing; timing optimization; Wiring

We introduce in this paper a new problem of post-mask engineering change order (ECO) timing optimization using spare-cell rewiring and present a two-phase framework for this problem. Spare-cell rewiring is a popular technique for incremental timing optimization and/or functional change after the pla...