ECO Timing Optimization Using Spare Cells and Technology Remapping

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 29; no. 5; pp. 697 - 710
• Main Authors: Ho, Kuan-Hsien, Chen, Yen-Pin, Fang, Jia-Wei, Chang, Yao-Wen
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Computer bugs; Cost function; Design engineering; Design optimization; Dynamic programming; Dynamics; Engineering change order (ECO); gate sizing; Heuristic algorithms; Integrated circuit technology; Optimization; physical design; Rewiring; Space technology; spare cells; Studies; technology remapping; Time measurements; Time to market; Timing; timing optimization; Wiring
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2010.2043573

We introduce in this paper a new problem of post-mask engineering change order (ECO) timing optimization using spare-cell rewiring and present a two-phase framework for this problem. Spare-cell rewiring is a popular technique for incremental timing optimization and/or functional change after the placement stage. The spare-cell rewiring problem is very challenging because of its dynamic wiring cost nature for selecting a spare cell, while the existing related problems consider only static wiring cost: once a standard cell is placed, its physical location is fixed and so is its wiring cost. For the spare-cell rewiring problem, each rewiring could make some spare cells become ordinary standard cells and some standard cells become new spare cells simultaneously. As a result, the wiring cost becomes dynamic and further complicates the optimization process. For the addressed problem, we present a two-phase framework of 1) buffer insertion and gate sizing followed by 2) technology remapping. For Phase 1, we present a dynamic programming algorithm considering the dynamic cost, called dynamic cost programming, for the ECO timing optimization with spare cells. Without loss of solution optimality, we further present an effective pruning method by selecting spare cells only inside an essential bounding polygon to reduce the solution space. For those ECO timing paths that cannot be fixed during Phase 1, we apply technology remapping on the spare cells to restructure the circuit to fix the timing violations. The whole framework is integrated into a commercial design flow. Experimental results based on five industry benchmarks show that our method is very effective and efficient in fixing the timing violations of ECO paths.