A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors

Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and-accumulate (MAC) operations of artificial intelligence (AI) chips. This work presents an static random access memory (SRAM) CIM unit-macro using: 1) compact-rule compatible twin-8T (T8T) cells for w...

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Published in	IEEE journal of solid-state circuits Vol. 55; no. 1; pp. 189 - 202
Main Authors	Si, Xin, Chen, Jia-Jing, Tu, Yung-Ning, Huang, Wei-Hsing, Wang, Jing-Hong, Chiu, Yen-Cheng, Wei, Wei-Chen, Wu, Ssu-Yen, Sun, Xiaoyu, Liu, Rui, Yu, Shimeng, Liu, Ren-Shuo, Hsieh, Chih-Cheng, Tang, Kea-Tiong, Li, Qiang, Chang, Meng-Fan
Format	Journal Article
Language	English
Published	New York IEEE 01.01.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects	Artificial intelligence Artificial intelligence (AI) Common Information Model (computing) computation-in-memory (CIM) convolutional neural network (CNN) Energy efficiency Kernel Mapping Power demand Power efficiency Program processors Random access memory SRAM cells Static random access memory Twin 8T (T8T)
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Abstract	Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and-accumulate (MAC) operations of artificial intelligence (AI) chips. This work presents an static random access memory (SRAM) CIM unit-macro using: 1) compact-rule compatible twin-8T (T8T) cells for weighted CIM MAC operations to reduce area overhead and vulnerability to process variation; 2) an even-odd dual-channel (EODC) input mapping scheme to extend input bandwidth; 3) a two's complement weight mapping (C2WM) scheme to enable MAC operations using positive and negative weights within a cell array in order to reduce area overhead and computational latency; and 4) a configurable global-local reference voltage generation (CGLRVG) scheme for kernels of various sizes and bit precision. A 64 <inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> 60 b T8T unit-macro with 1-, 2-, 4-b inputs, 1-, 2-, 5-b weights, and up to 7-b MAC-value (MACV) outputs was fabricated as a test chip using a foundry 55-nm process. The proposed SRAM-CIM unit-macro achieved access times of 5 ns and energy efficiency of 37.5-45.36 TOPS/W under 5-b MACV output.
AbstractList	Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and-accumulate (MAC) operations of artificial intelligence (AI) chips. This work presents an static random access memory (SRAM) CIM unit-macro using: 1) compact-rule compatible twin-8T (T8T) cells for weighted CIM MAC operations to reduce area overhead and vulnerability to process variation; 2) an even–odd dual-channel (EODC) input mapping scheme to extend input bandwidth; 3) a two’s complement weight mapping (C2WM) scheme to enable MAC operations using positive and negative weights within a cell array in order to reduce area overhead and computational latency; and 4) a configurable global–local reference voltage generation (CGLRVG) scheme for kernels of various sizes and bit precision. A 64 [Formula Omitted] 60 b T8T unit-macro with 1-, 2-, 4-b inputs, 1-, 2-, 5-b weights, and up to 7-b MAC-value (MACV) outputs was fabricated as a test chip using a foundry 55-nm process. The proposed SRAM-CIM unit-macro achieved access times of 5 ns and energy efficiency of 37.5–45.36 TOPS/W under 5-b MACV output. Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and-accumulate (MAC) operations of artificial intelligence (AI) chips. This work presents an static random access memory (SRAM) CIM unit-macro using: 1) compact-rule compatible twin-8T (T8T) cells for weighted CIM MAC operations to reduce area overhead and vulnerability to process variation; 2) an even-odd dual-channel (EODC) input mapping scheme to extend input bandwidth; 3) a two's complement weight mapping (C2WM) scheme to enable MAC operations using positive and negative weights within a cell array in order to reduce area overhead and computational latency; and 4) a configurable global-local reference voltage generation (CGLRVG) scheme for kernels of various sizes and bit precision. A 64 <inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> 60 b T8T unit-macro with 1-, 2-, 4-b inputs, 1-, 2-, 5-b weights, and up to 7-b MAC-value (MACV) outputs was fabricated as a test chip using a foundry 55-nm process. The proposed SRAM-CIM unit-macro achieved access times of 5 ns and energy efficiency of 37.5-45.36 TOPS/W under 5-b MACV output.
Author	Chiu, Yen-Cheng Sun, Xiaoyu Wu, Ssu-Yen Yu, Shimeng Liu, Ren-Shuo Wang, Jing-Hong Liu, Rui Li, Qiang Chen, Jia-Jing Huang, Wei-Hsing Wei, Wei-Chen Tang, Kea-Tiong Tu, Yung-Ning Chang, Meng-Fan Hsieh, Chih-Cheng Si, Xin
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Snippet	Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and-accumulate (MAC) operations of artificial intelligence...
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SubjectTerms	Artificial intelligence Artificial intelligence (AI) Common Information Model (computing) computation-in-memory (CIM) convolutional neural network (CNN) Energy efficiency Kernel Mapping Power demand Power efficiency Program processors Random access memory SRAM cells Static random access memory Twin 8T (T8T)
Title	A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors
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