Characteristics of bottom-gate low temperature nanocrystalline silicon thin film transistor fabricated by hydrogen annealing of gate dielectric layer
Thin film transistors having nanocrystalline silicon as an active layer were fabricated by catalytic-CVD at a low process temperature (≤ 200 °C). The tri-layer of the bottom-gate TFT was deposited continuously inside the Cat-CVD reactor. In order to improve the quality of the gate dielectric layer a...
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Published in | Thin solid films Vol. 518; no. 22; pp. 6311 - 6314 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
Amsterdam
Elsevier B.V
01.09.2010
Elsevier |
Subjects | |
Online Access | Get full text |
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Summary: | Thin film transistors having nanocrystalline silicon as an active layer were fabricated by catalytic-CVD at a low process temperature (≤
200
°C). The tri-layer of the bottom-gate TFT was deposited continuously inside the Cat-CVD reactor. In order to improve the quality of the gate dielectric layer an in-situ hydrogen annealing step was introduced in between the silicon nitride and the nanocrystalline silicon deposition steps. The in-situ hydrogen annealing was effective in reducing the hysteresis in the C–V characteristics and in enhancing the breakdown voltage by decreasing the defects inside the SiN
x
film. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0040-6090 1879-2731 |
DOI: | 10.1016/j.tsf.2010.03.057 |