Exploiting Error Characteristic to Optimize Read Voltage for 3-D NAND Flash Memory

• Published in: IEEE transactions on electron devices Vol. 67; no. 12; pp. 5490 - 5496
• Main Authors: Zhang, Meng, Wu, Fei, Yu, Qin, Liu, Weihua, Wang, Yifan, Xie, Changsheng
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 3-D triple-level cell (TLC) NAND flash; Bit error rate; Computer storage devices; Error analysis; Field programmable gate arrays; Flash memories; Flash memory (computers); Interference; Logic gates; Optimization; P/E cycles; raw bit error rate (RBER); read reference voltage (RRV); retention periods; Threshold voltage

3-D NAND flash memory has become increasingly popular nonvolatile storage devices due to large capacity and high performance. With the increase of program/erase (P/E) cycles and retention periods, the threshold voltage distribution of 3-D NAND flash memory is prone to shift such that it is difficult...