Exploiting Error Characteristic to Optimize Read Voltage for 3-D NAND Flash Memory - Zhang, Meng; Wu, Fei; Yu, Qin; Liu, Weihua; Wang, Yifan; Xie, Changsheng (IEEE transactions on electron devices, 2020)
Keywords: 3-D triple-level cell (TLC) NAND flash; Bit error rate; Computer storage devices; Error analysis; Field programmable gate arrays; Flash memories; Flash memory (computers); Interference; Logic gates; Optimization; P/E cycles; raw bit error rate (RBER); read reference voltage (RRV); retention periods; Threshold voltage