Steep Switching Hybrid Phase Transition FETs (Hyper-FET) for Low Power Applications: A Device-Circuit Co-design Perspective-Part I

• Published in: IEEE transactions on electron devices Vol. 64; no. 3; pp. 1350 - 1357
• Main Authors: Aziz, Ahmedullah, Shukla, Nikhil, Datta, Suman, Gupta, Sumeet Kumar
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Boltzmann limit; Circuit design; Co-design; correlated material; Field effect transistors; hybrid-phase-transition FETs (Hyper-FET); insulator–metal transition; Integrated circuit modeling; Ions; Performance evaluation; phase transition; Phase transitions; Resistance; steep slope; Switches
• DOI: 10.1109/TED.2016.2642884
• ISSN: 0018-9383

Hybrid-phase-transition FETs (Hyper-FETs) are recently proposed steep switching devices that utilize the phase transition materials (PTM) to achieve a boost in the ratio of ON (I ON ) and OFF currents (I OFF ). Prototypical demonstrations of the Hyper-FET have shown performance improvement in comparison with conventional transistors, which motivates the evaluation of its device-circuit design space. In part I, we analyze the device aspects establishing the effects of the resistivity and phase transition thresholds of the PTM on the characteristics of Hyper-FETs. Our analysis shows that the ratio of insulating and metallic state resistivity (ρ INS and ρ MET , respectively) of the PTM needs to be higher than the ION/IOFF of its host transistor to achieve performance improvement in Hyper-FET. For a host transistor with I OFF = 0.051μA/μm and I ON = 191.5μA/μm, ρ MET <;~ 2 × 10 -3 Ω.cm and ~7.5 Ω.cm<; ρ INS <; 20000Ω.cm is required to achieve proper device functionality with a boost in I ON /I OFF . Additionally, we establish the ranges of phase transition thresholds that yield proper functionality of the Hyper-FETs considering different I OFF targets. The methodology of choosing appropriate PTM geometry to achieve the target device characteristics is also described. We show that with proper design, Hyper-FETs achieve 94% larger I ON at iso-I OFF compared with a FinFET. We examine the circuit design aspects of Hyper-FET in part II.