An Optimal Partitioning and Floor Planning for VLSI Circuit Design Based on a Hybrid Bio-Inspired Whale Optimization and Adaptive Bird Swarm Optimization (WO-ABSO) Algorithm

• Published in: Journal of circuits, systems, and computers Vol. 32; no. 8
• Main Authors: Karthick, R., Senthilselvi, A., Meenalochini, P., Senthil Pandi, S
• Format: Journal Article
• Language: English
• Published: Singapore World Scientific Publishing Company 30.05.2023; World Scientific Publishing Co. Pte., Ltd
• Subjects: Algorithms; Benchmarks; Biomimetics; Circuit design; Delay; Design optimization; Floorplans; Large scale integration; Partitioning; Planning; Very large scale integration; Adaptive Bird Swarm Optimization (ABSO) algorithm; Whale Optimization (WO); Partitioning and floor planning; VLSI circuit design
• DOI: 10.1142/S0218126623502730
• ISSN: 0218-1266

Partitioning and Floor Planning are two of the design processes in the VLSI design and are used to reduce the size of the circuit. Area and interconnect length reduction are the key goals for physical design automation of very large-scale integration chips in VLSI physical design optimization. The aim of decreasing the area and interconnect length is to decrease the integrated chip’s size. To achieve the above objective and to achieve the aforementioned goal, an ideal solution for physical design components, like partitioning, floor planning must be found. The existing methods did not provide the sufficient results for Partition and Floor Plan. Therefore, in this paper, an Optimal Partitioning and Floor Planning for the VLSI Circuit Design based on Hybrid Bio-inspired Whale Optimization and Adaptive Bird Swarm Optimization (WO-ABSO) Algorithm are proposed. The goal of hybrid WO-ABSO algorithm for decreasing the delay for partitioning, decreasing the area for floor planning, decreasing the delay, wire length in floor planning has indefinite influence on other criteria, such as power and speed. Here, the circuit partitioning problem is optimized using whale optimization algorithm and the floor planning problem is optimized under ABSO algorithm. The benchmark tests included test cases from Microelectronics Center of North Carolina (MCNC) benchmark circuits. The proposed hybrid WO-ABSO algorithm attains lower area, lower delay, and lower power usage compared with the existing methods.