Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding

•Decimal arithmetic adders that accept BCC (radix-1000) encoded operands and produce BCC results are proposed.•Six different conditional speculation options are studied.•The best proposed design show advantages in area (17%), power (13%) and PDP (14%) measures, over the best previous relevant work....

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Published inComputers & electrical engineering Vol. 50; pp. 39 - 53
Main Authors Dorrigiv, M., Jaberipur, G.
Format Journal Article
LanguageEnglish
Published Elsevier Ltd 01.02.2016
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ISSN0045-7906
1879-0755
DOI10.1016/j.compeleceng.2015.12.002

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Abstract •Decimal arithmetic adders that accept BCC (radix-1000) encoded operands and produce BCC results are proposed.•Six different conditional speculation options are studied.•The best proposed design show advantages in area (17%), power (13%) and PDP (14%) measures, over the best previous relevant work. Decimal arithmetic circuits, based on IEEE-754-2008 standard, commonly use 10-bit densely-packed-decimal (DPD) encoding of three binary-coded-decimal (BCD) digits. Binary-coded-chiliad (BCC) encoding, as storage (arithmetic) efficient as DPD (BCD), equivalently packs three BCD digits. No unpacking/packing to/from BCD (entailing extra delay/power) per each arithmetic operation (required in case of DPD), are necessary for BCC. Therefore, while abiding to DPD standard, we are motivated to design decimal arithmetic operators that accept BCC operands and produce BCC results. As such, DPD data from memory or input devices are converted to BCC, manipulated in BCC and stored in the BCC register file, during multi-operation decimal computations, and converted back to DPD only on reporting results to memory or output devices. In this paper, following a previous simple mixed BCC/binary adder, we design and synthesize more efficient ones, and compare them with previous relevant BCD and BCC adders to show advantages in area, and power. [Display omitted]
AbstractList Decimal arithmetic circuits, based on IEEE-754-2008 standard, commonly use 10-bit densely-packed-decimal (DPD) encoding of three binary-coded-decimal (BCD) digits. Binary-coded-chiliad (BCC) encoding, as storage (arithmetic) efficient as DPD (BCD), equivalently packs three BCD digits. No unpacking/packing to/from BCD (entailing extra delay/power) per each arithmetic operation (required in case of DPD), are necessary for BCC. Therefore, while abiding to DPD standard, we are motivated to design decimal arithmetic operators that accept BCC operands and produce BCC results. As such, DPD data from memory or input devices are converted to BCC, manipulated in BCC and stored in the BCC register file, during multi-operation decimal computations, and converted back to DPD only on reporting results to memory or output devices. In this paper, following a previous simple mixed BCC/binary adder, we design and synthesize more efficient ones, and compare them with previous relevant BCD and BCC adders to show advantages in area, and power.
•Decimal arithmetic adders that accept BCC (radix-1000) encoded operands and produce BCC results are proposed.•Six different conditional speculation options are studied.•The best proposed design show advantages in area (17%), power (13%) and PDP (14%) measures, over the best previous relevant work. Decimal arithmetic circuits, based on IEEE-754-2008 standard, commonly use 10-bit densely-packed-decimal (DPD) encoding of three binary-coded-decimal (BCD) digits. Binary-coded-chiliad (BCC) encoding, as storage (arithmetic) efficient as DPD (BCD), equivalently packs three BCD digits. No unpacking/packing to/from BCD (entailing extra delay/power) per each arithmetic operation (required in case of DPD), are necessary for BCC. Therefore, while abiding to DPD standard, we are motivated to design decimal arithmetic operators that accept BCC operands and produce BCC results. As such, DPD data from memory or input devices are converted to BCC, manipulated in BCC and stored in the BCC register file, during multi-operation decimal computations, and converted back to DPD only on reporting results to memory or output devices. In this paper, following a previous simple mixed BCC/binary adder, we design and synthesize more efficient ones, and compare them with previous relevant BCD and BCC adders to show advantages in area, and power. [Display omitted]
Author Jaberipur, G.
Dorrigiv, M.
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10.1109/TC.2011.43
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Keywords Speculative decimal addition
Decimal computer arithmetic
Densely packed decimal encoding
Mixed decimal/binary adder
Binary coded chiliad encoding
Language English
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Snippet •Decimal arithmetic adders that accept BCC (radix-1000) encoded operands and produce BCC results are proposed.•Six different conditional speculation options...
Decimal arithmetic circuits, based on IEEE-754-2008 standard, commonly use 10-bit densely-packed-decimal (DPD) encoding of three binary-coded-decimal (BCD)...
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SubjectTerms Arithmetic
Binary coded chiliad encoding
Body centered cubic lattice
Decimal computer arithmetic
Decimals
Densely packed decimal encoding
Design engineering
Digits
Electric power generation
Encoding
Mixed decimal/binary adder
Speculative decimal addition
Title Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding
URI https://dx.doi.org/10.1016/j.compeleceng.2015.12.002
https://www.proquest.com/docview/1825458982
Volume 50
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