Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 14; no. 9; pp. 986 - 997
• Main Authors: Cong, J., Guoling Han, Zhiru Zhang
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.09.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Application specific processors; Applied sciences; Architecture; Bandwidth; Communication system control; Computers, microcomputers; Configurable; Data analysis; Data bandwidth optimization; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Hardware; Input-output equipment; Integrated circuits; Integrated circuits by function (including memories and processors); Microarchitecture; Optimization; Optimizing compilers; Processors; Reconfigurable architectures; Reconfigurable logic; register allocation; Registers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Shadows; Very large scale integration; Performance evaluation; Compiler; Data analysis; Processor; Instruction sets; Data transmission; optimizing compilers; Algorithm; register allocation; Boarded computer; Data bandwidth optimization; Coding; Integrated circuit; Compiler optimization; Reconfigurable architectures; Custom circuit; Cost lowering; Quantitative analysis

Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in the tools and methodologies of automatic instruction set extension for configurable processors, the limited data bandwidth...