Jointly Designed Architecture-Aware LDPC Convolutional Codes and Memory-Based Shuffled Decoder Architecture

• Published in: IEEE transactions on signal processing Vol. 60; no. 8; pp. 4387 - 4402
• Main Authors: UENG, Yeong-Luh, WANG, Yu-Luen, KAN, Li-Sheng, YANG, Chung-Jay, SU, Yung-Hsiang
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.08.2012; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Architecture; Bit error rate; Clocks; Codes; Coding, codes; Convolutional codes (CCs); Cost engineering; Decoders; Decoding; Detection, estimation, filtering, equalization, prediction; Equations; Exact sciences and technology; Information, signal and communications theory; Iterative decoding; low-density parity-check (LDPC) convolutional codes; Networks; Permutations; Processors; Program processors; Shift registers; Signal and communications theory; Signal, noise; Strontium; Telecommunications and information theory; Transaction processing; VLSI; Cost minimization; Error estimation; Information rate; Iterative method; s—Convolutional codes (CCs); Clock; Time variation; Implementation; Complementary MOS technology; Parity check codes; High rate transmission; VLSI circuit; Convolutional code; VLSI; Decoding; low-density s parity-check (LDPC) convolutional codes; Information transmission; Message passing; Storage management; Signal processing; Production cost; Error correcting code; Feasibility; Parallelization; Parity check
• DOI: 10.1109/TSP.2012.2197749
• ISSN: 1053-587X

In this paper, we jointly design architecture-aware (AA) low-density parity-check convolutional codes (LDPC-CCs) and the associated memory-based decoder architecture based on shuffled message-passing decoding (MPD). We propose a method for constructing AA-LDPC-CCs that can facilitate the design of a memory-based shuffled decoder using parallelization in both iteration and node dimensions. Through the use of shuffled MPD, the number of base processors and, hence, the decoder area is significantly reduced, since a fewer number of iterations is required in order to achieve a desired error performance. In addition, the use of memory instead of registers minimizes the implementation cost of each base processor. In the memory-based decoder, collisions in memory access can be avoided and the difficulty in exchanging information between iterations (processors) is overcome by using simple permutation networks. To demonstrate the feasibility of the proposed techniques, we constructed a time-varying (479, 3, 6) AA-LDPC-CC and implemented its associated shuffled decoder using a 90-nm CMOS process. This decoder comprises 11 processors, occupies an area of 5.36 , and achieves an information throughput of 1.025 Gbps at a clock frequency of 256.4 MHz based on post-layout results.