The Hysteretic Ferroelectric Tunnel FET

• Published in: IEEE transactions on electron devices Vol. 57; no. 12; pp. 3518 - 3524
• Main Authors: Ionescu, A M, Lattanzio, L, Salvatore, G A, De Michielis, L, Boucart, K, Bouvet, D
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.12.2010; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuit properties; Devices; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Ferroelectric devices; Ferroelectric FET; Ferroelectric materials; Ferroelectricity; FETs; Gates; Hysteresis; Iron; Magnetic and optical mass memories; memory; Molecular electronics, nanoelectronics; MOSFET circuits; nanoelectronic switch; Nanoelectronics; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Stacks; Storage and reproduction of information; Studies; Switching, multiplexing, switched capacity circuits; Temperature measurement; Transistors; tunnel FET; Tunneling; Tunnels (transportation); Memory devices; memory; Depletion layer; Transistor gate; IV-VI compound; Nanoelectronics; Silicon on insulator technology; Hysteresis loop; III-VI compound; p type semiconductor; Vinylidene fluoride polymer; Selector switch; Electrical characteristic; Ultrathin films; nanoelectronic switch; Retention factor; Multiple layer; Ferroelectric FET; tunnel FET; Temperature measurement; Field effect transistor; Ferroelectric materials; Silicon oxides; Numerical simulation; Low-power electronics; Alumina; Tunneling device; Room temperature
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2010.2079531

We present the fabrication and the electrical characterization of ferroelectric tunnel FETs (Fe-TFETs). This novel family of hysteretic switches combines the low subthreshold power of band-to-band tunneling devices with the retention characteristics of Fe gate stacks, offering some interesting features for future one-transistor (1T) memory cells. We report I on /I off larger than 10 5 and I off on the order of 100 fA/μm in micrometer-scale p-type Fe-TFETs fabricated on ultrathin-film (fully depleted) silicon-on-insulator substrates with a SiO 2 /Al 2 O 3 / PVDF gate stack processed at low temperature. The hysteretic characteristics of the TFETs with Fe gate stacks are revealed by static experiments, and the principle of the proposed device is further confirmed by 2-D calibrated numerical simulations. Low temperature measurements down to 77 K confirm the reduced sensitivity of the TFET subthreshold swing to temperature and distinguish them from fabricated reference Fe metal-oxide-semiconductor FETs. Finally, we investigate the potential of Fe-TFETs as 1T memory devices and find retention times on the order of a few minutes at room temperature.