Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets
This paper studies the problems of optimizing power dissipation for simultaneous buffer insertion/sizing and uniform wire sizing (BISUWS), and simultaneous buffer insertion/sizing and tapered wire sizing (BISTWS). For BISUWS, we analyze the optimal total power dissipation under the delay constraints...
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| Published in | IEEE transactions on computer-aided design of integrated circuits and systems Vol. 24; no. 12; pp. 1915 - 1924 |
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| Main Authors | , , , |
| Format | Journal Article |
| Language | English |
| Published |
New York
IEEE
01.12.2005
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subjects | |
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| Abstract | This paper studies the problems of optimizing power dissipation for simultaneous buffer insertion/sizing and uniform wire sizing (BISUWS), and simultaneous buffer insertion/sizing and tapered wire sizing (BISTWS). For BISUWS, we analyze the optimal total power dissipation under the delay constraints as well as the power-delay tradeoff. For BISTWS, we study the problems of minimizing power dissipation with optimal delay constraints or with a given delay penalty. We derive optimal solutions for both cases. These solutions can be used to efficiently estimate the power dissipation for long single wires in the interconnect designs. |
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| AbstractList | This paper studies the problems of optimizing power dissipation for simultaneous buffer insertion/sizing and uniform wire sizing (BISUWS), and simultaneous buffer insertion/sizing and tapered wire sizing (BISTWS). For BISUWS, we analyze the optimal total power dissipation under the delay constraints as well as the power-delay tradeoff. For BISTWS, we study the problems of minimizing power dissipation with optimal delay constraints or with a given delay penalty. We derive optimal solutions for both cases. These solutions can be used to efficiently estimate the power dissipation for long single wires in the interconnect designs. |
| Author | Jin Liu Ruiming Li Xuan Zeng Dian Zhou |
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| Snippet | This paper studies the problems of optimizing power dissipation for simultaneous buffer insertion/sizing and uniform wire sizing (BISUWS), and simultaneous... |
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| StartPage | 1915 |
| SubjectTerms | Application specific integrated circuits Buffer insertion Delay effects Digital integrated circuits Educational technology Integrated circuit interconnections Laboratories power Power dissipation Research and development simultaneous buffer insertion/sizing and wire sizing Very large scale integration Wire wire sizing |
| Title | Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets |
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