eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip

• Published in: Chronic diseases and translational medicine Vol. 8; no. 3; pp. 148 - 162
• Main Authors: Beldachi, Arash Farhadi, Hollis, Simon, Nunez-Yanez, Jose L
• Format: Journal Article
• Language: English
• Published: Stevenage The Institution of Engineering and Technology 01.05.2014; Institution of Engineering and Technology; John Wiley & Sons, Inc
• Subjects: Algorithms; application behaviour; Applied sciences; Circuit properties; Communication; Design; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Error correction & detection; Exact sciences and technology; eXtended Torus routing algorithm for networks‐on‐chip; Field programmable gate arrays; FPGA; Hierarchies; inner‐torus building blocks; Integrated circuits; mesh generation; mesh topology; network‐on‐chip; nonregular global topologies; Performance evaluation; resource availability; Routers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; topology; XTRANC algorithm; network-on-chip; eXtended Torus routing algorithm for networks-on-chip; application behaviour; inner-torus building blocks; XTRANC algorithm; field programmable gate arrays; nonregular global topologies; FPGA; topology; mesh generation; resource availability; mesh topology; Performance evaluation; Interconnection network; Dynamic characteristic; Meshed network; Network architecture; Field programmable gate array; System on a chip; Algorithm; Centralized control; Deadlock; Integrated circuit; Reconfigurable architectures; Speech processing; Execution time
• ISSN: 1751-8601; 1751-861X; 2095-882X; 1751-861X; 2589-0514
• DOI: 10.1049/iet-cdt.2013.0087

This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-networks to increase the mesh performance. The sub-networks can generate non-regular global topologies which are also supported by the XTRANC algorithm. XTRANC is especially suitable for dynamically reconfigurable networks mapped to commercial FPGAs in which additional links are added to the mesh topology at run-time to reduce congestion depending on application behaviour and resource availability. XTRANC allows the insertion of links as requested by different parts of the application without centralized control and this research shows that despite this dynamic behaviour the routing algorithm remains deadlock free.