Calibrating sample and hold stages with pruned Volterra kernels

Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal-to-noise-and-distortion ratio (SNDR): CMOS switch non-idealities, amplifier no...

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Published inElectronics letters Vol. 51; no. 25; pp. 2094 - 2096
Main Authors Centurelli, F, Monsurrò, P, Rosato, F, Ruscio, D, Trifiletti, A
Format Journal Article
LanguageEnglish
Published The Institution of Engineering and Technology 10.12.2015
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Abstract Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal-to-noise-and-distortion ratio (SNDR): CMOS switch non-idealities, amplifier nonlinearity, and incomplete settling. It is possible to model and correct distortions using Volterra kernels, which can be rather resource-consuming as the number of parameters to estimate rapid increases with the order and length of the kernels. In this reported work, it is shown that a switched capacitor SHA, simulated using the 45 nm process by STMicroelectronics, can be calibrated to achieve a 10–24 dB improvement in SNDR. Computational costs are kept low using a different lag value for each kernel, and iteratively pruning the elements of the Volterra kernels which affect linearity the least. A technique for estimation and out-of-sample validation is presented and robustness checks are performed. A performance gain of 8.5 dB can be achieved with as few as 17 correction parameters, while 21 coefficients are enough to gain 12.2 dB, and 36 to gain 18.4 dB.
AbstractList Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal-to-noise-and-distortion ratio (SNDR): CMOS switch non-idealities, amplifier nonlinearity, and incomplete settling. It is possible to model and correct distortions using Volterra kernels, which can be rather resource-consuming as the number of parameters to estimate rapid increases with the order and length of the kernels. In this reported work, it is shown that a switched capacitor SHA, simulated using the 45 nm process by STMicroelectronics, can be calibrated to achieve a 10–24 dB improvement in SNDR. Computational costs are kept low using a different lag value for each kernel, and iteratively pruning the elements of the Volterra kernels which affect linearity the least. A technique for estimation and out-of-sample validation is presented and robustness checks are performed. A performance gain of 8.5 dB can be achieved with as few as 17 correction parameters, while 21 coefficients are enough to gain 12.2 dB, and 36 to gain 18.4 dB.
Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal‐to‐noise‐and‐distortion ratio (SNDR): CMOS switch non‐idealities, amplifier nonlinearity, and incomplete settling. It is possible to model and correct distortions using Volterra kernels, which can be rather resource‐consuming as the number of parameters to estimate rapid increases with the order and length of the kernels. In this reported work, it is shown that a switched capacitor SHA, simulated using the 45 nm process by STMicroelectronics, can be calibrated to achieve a 10–24 dB improvement in SNDR. Computational costs are kept low using a different lag value for each kernel, and iteratively pruning the elements of the Volterra kernels which affect linearity the least. A technique for estimation and out‐of‐sample validation is presented and robustness checks are performed. A performance gain of 8.5 dB can be achieved with as few as 17 correction parameters, while 21 coefficients are enough to gain 12.2 dB, and 36 to gain 18.4 dB.
Author Rosato, F
Ruscio, D
Centurelli, F
Trifiletti, A
Monsurrò, P
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Cites_doi 10.1109/TIM.2013.2295877
10.1109/JSTSP.2009.2020557
10.1109/JSTSP.2009.2020575
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Issue 25
Keywords gain 8.5 dB
pruned Volterra kernels
Volterra equations
iterative pruning
amplifier nonlinearity
deep submicron technology
gain 12.2 dB
sample and hold circuits
switched capacitor
correct distortions
sample and hold stages
STMicroelectronics
switched capacitor networks
CMOS integrated circuits
size 45 nm
calibration
CMOS switch nonideality
gain 18.4 dB
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Snippet Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are...
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StartPage 2094
SubjectTerms amplifier nonlinearity
calibration
Circuits and systems
CMOS integrated circuits
CMOS switch nonideality
correct distortions
deep submicron technology
gain 12.2 dB
gain 18.4 dB
gain 8.5 dB
iterative pruning
pruned Volterra kernels
sample and hold circuits
sample and hold stages
size 45 nm
STMicroelectronics
switched capacitor
switched capacitor networks
Volterra equations
Title Calibrating sample and hold stages with pruned Volterra kernels
URI http://digital-library.theiet.org/content/journals/10.1049/el.2015.3269
https://onlinelibrary.wiley.com/doi/abs/10.1049%2Fel.2015.3269
Volume 51
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