Calibrating sample and hold stages with pruned Volterra kernels
Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal-to-noise-and-distortion ratio (SNDR): CMOS switch non-idealities, amplifier no...
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Published in | Electronics letters Vol. 51; no. 25; pp. 2094 - 2096 |
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Main Authors | , , , , |
Format | Journal Article |
Language | English |
Published |
The Institution of Engineering and Technology
10.12.2015
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Abstract | Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal-to-noise-and-distortion ratio (SNDR): CMOS switch non-idealities, amplifier nonlinearity, and incomplete settling. It is possible to model and correct distortions using Volterra kernels, which can be rather resource-consuming as the number of parameters to estimate rapid increases with the order and length of the kernels. In this reported work, it is shown that a switched capacitor SHA, simulated using the 45 nm process by STMicroelectronics, can be calibrated to achieve a 10–24 dB improvement in SNDR. Computational costs are kept low using a different lag value for each kernel, and iteratively pruning the elements of the Volterra kernels which affect linearity the least. A technique for estimation and out-of-sample validation is presented and robustness checks are performed. A performance gain of 8.5 dB can be achieved with as few as 17 correction parameters, while 21 coefficients are enough to gain 12.2 dB, and 36 to gain 18.4 dB. |
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AbstractList | Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal-to-noise-and-distortion ratio (SNDR): CMOS switch non-idealities, amplifier nonlinearity, and incomplete settling. It is possible to model and correct distortions using Volterra kernels, which can be rather resource-consuming as the number of parameters to estimate rapid increases with the order and length of the kernels. In this reported work, it is shown that a switched capacitor SHA, simulated using the 45 nm process by STMicroelectronics, can be calibrated to achieve a 10–24 dB improvement in SNDR. Computational costs are kept low using a different lag value for each kernel, and iteratively pruning the elements of the Volterra kernels which affect linearity the least. A technique for estimation and out-of-sample validation is presented and robustness checks are performed. A performance gain of 8.5 dB can be achieved with as few as 17 correction parameters, while 21 coefficients are enough to gain 12.2 dB, and 36 to gain 18.4 dB. Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal‐to‐noise‐and‐distortion ratio (SNDR): CMOS switch non‐idealities, amplifier nonlinearity, and incomplete settling. It is possible to model and correct distortions using Volterra kernels, which can be rather resource‐consuming as the number of parameters to estimate rapid increases with the order and length of the kernels. In this reported work, it is shown that a switched capacitor SHA, simulated using the 45 nm process by STMicroelectronics, can be calibrated to achieve a 10–24 dB improvement in SNDR. Computational costs are kept low using a different lag value for each kernel, and iteratively pruning the elements of the Volterra kernels which affect linearity the least. A technique for estimation and out‐of‐sample validation is presented and robustness checks are performed. A performance gain of 8.5 dB can be achieved with as few as 17 correction parameters, while 21 coefficients are enough to gain 12.2 dB, and 36 to gain 18.4 dB. |
Author | Rosato, F Ruscio, D Centurelli, F Trifiletti, A Monsurrò, P |
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Cites_doi | 10.1109/TIM.2013.2295877 10.1109/JSTSP.2009.2020557 10.1109/JSTSP.2009.2020575 |
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Keywords | gain 8.5 dB pruned Volterra kernels Volterra equations iterative pruning amplifier nonlinearity deep submicron technology gain 12.2 dB sample and hold circuits switched capacitor correct distortions sample and hold stages STMicroelectronics switched capacitor networks CMOS integrated circuits size 45 nm calibration CMOS switch nonideality gain 18.4 dB |
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References | Schmidt, C.A.; Lifschitz, O.; Cousseau, J.E.; Figueroa, J.L.; Julian, P. (C4) 2014; 63 Satarzadeh, P.; Levy, B.C.; Hurst, P.J. (C3) 2009; 3 Nikaeen, P.; Murmann, B. (C2) 2009; 3 2009; 3 2014; 63 2000 Mathews V.G. (e_1_2_9_2_1) 2000 Nikaeen P. (e_1_2_9_3_1) 2009; 3 Satarzadeh P. (e_1_2_9_4_1) 2009; 3 Schmidt C.A. (e_1_2_9_5_1) 2014; 63 |
References_xml | – volume: 3 start-page: 454 issue: 3 year: 2009 end-page: 471 ident: C3 article-title: Digital calibration of a nonlinear S/H publication-title: IEEE J. Sel. Top. Signal Process. contributor: fullname: Satarzadeh, P.; Levy, B.C.; Hurst, P.J. – volume: 3 start-page: 499 issue: 3 year: 2009 end-page: 508 ident: C2 article-title: Digital compensation of dynamic acquisition errors at the front-end of high-performance A/D converters publication-title: IEEE J. Sel. Top. Signal Process. contributor: fullname: Nikaeen, P.; Murmann, B. – volume: 63 start-page: 658 issue: 3 year: 2014 end-page: 666 ident: C4 article-title: Methodology and measurement setup for analog-to-digital converter postcompensation publication-title: IEEE Trans. Instrum. Meas. contributor: fullname: Schmidt, C.A.; Lifschitz, O.; Cousseau, J.E.; Figueroa, J.L.; Julian, P. – year: 2000 – volume: 63 start-page: 658 issue: 3 year: 2014 end-page: 666 article-title: Methodology and measurement setup for analog‐to‐digital converter postcompensation publication-title: IEEE Trans. Instrum. Meas. – volume: 3 start-page: 454 issue: 3 year: 2009 end-page: 471 article-title: Digital calibration of a nonlinear S/H publication-title: IEEE J. Sel. Top. Signal Process. – volume: 3 start-page: 499 issue: 3 year: 2009 end-page: 508 article-title: Digital compensation of dynamic acquisition errors at the front‐end of high‐performance A/D converters publication-title: IEEE J. Sel. Top. Signal Process. – volume-title: Polynomial signal processing year: 2000 ident: e_1_2_9_2_1 contributor: fullname: Mathews V.G. – volume: 63 start-page: 658 issue: 3 year: 2014 ident: e_1_2_9_5_1 article-title: Methodology and measurement setup for analog‐to‐digital converter postcompensation publication-title: IEEE Trans. Instrum. Meas. doi: 10.1109/TIM.2013.2295877 contributor: fullname: Schmidt C.A. – volume: 3 start-page: 454 issue: 3 year: 2009 ident: e_1_2_9_4_1 article-title: Digital calibration of a nonlinear S/H publication-title: IEEE J. Sel. Top. Signal Process. doi: 10.1109/JSTSP.2009.2020557 contributor: fullname: Satarzadeh P. – volume: 3 start-page: 499 issue: 3 year: 2009 ident: e_1_2_9_3_1 article-title: Digital compensation of dynamic acquisition errors at the front‐end of high‐performance A/D converters publication-title: IEEE J. Sel. Top. Signal Process. doi: 10.1109/JSTSP.2009.2020575 contributor: fullname: Nikaeen P. |
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Snippet | Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are... |
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SubjectTerms | amplifier nonlinearity calibration Circuits and systems CMOS integrated circuits CMOS switch nonideality correct distortions deep submicron technology gain 12.2 dB gain 18.4 dB gain 8.5 dB iterative pruning pruned Volterra kernels sample and hold circuits sample and hold stages size 45 nm STMicroelectronics switched capacitor switched capacitor networks Volterra equations |
Title | Calibrating sample and hold stages with pruned Volterra kernels |
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