Effects of gate dielectric composition on the performance of organic thin-film devices

• Published in: Synthetic metals Vol. 162; no. 7-8; pp. 598 - 604
• Main Authors: Das, Sujoy, Lee, Junghyun, Lim, Taehoon, Choi, Youngill, Park, Yong Sun, Pyo, Seungmoon
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01.05.2012; Elsevier
• Subjects: Application fields; Applied sciences; Cross-linking reaction; Electronics; Exact sciences and technology; Organic complementary inverter; Organic field-effect transistors; Organic semiconductors; Polymer gate dielectrics; Polymer industry, paints, wood; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Technology of polymers; Transistors; Organic complementary inverter; Organic semiconductors; Cross-linking reaction; Polymer gate dielectrics; Organic field-effect transistors; Structure effect; Pentacene; Gate voltage; Voltage current curve; Dielectric materials; Copper complex; Surface topography; Triazine derivative polymer; Experimental study; Styrene(hydroxy) polymer; Field effect transistor; Metallophthalocyanine; Linear polymer; Crosslinked polymer; Drain current; Transistor inverter
• ISSN: 0379-6779; 1879-3290
• DOI: 10.1016/j.synthmet.2012.01.020

► Gate dielectrics affected the growth of organic semiconductor and OFET performance. ► Devices’ characteristics were significantly affected by OH group in the gate dielectric. ► Use of the optimized gate dielectric resulted in a higher performing OFET and complementary inverter. Four poly(4-vinyl phenol) based gate dielectrics were tested to optimize the performance of pentacene organic field-effect transistors. The dielectrics’ surface tensions, Fourier transform infrared spectra, capacitances and leakage currents were measured. The optimal dielectric allowed the transistor to show negligible hysteresis with high performance even in ambient conditions. A complementary inverter was fabricated by integrating in single substrate pentacene (p-type) and F16CuPc (n-type) OFETs containing the optimized gate dielectric. Its voltage transfer curve showed almost symmetric noise margin; it showed a logic threshold of 22.5V and a maximum voltage gain (δVout/δVin) of 6.2 at Vin=22.5V.