A single-chip CIF 30-Hz, H261, H263, and H263+ video encoder/decoder with embedded display controller

A single-chip video codec with embedded display controller for videotelephony applications is described. It encodes and decodes simultaneously up to 30 CIF pictures per second according to video-conferencing recommendations H261, H263 (all five options), and H263+ (six additional options). The die a...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 34; no. 11; pp. 1627 - 1633
Main Authors Harrand, M., Sanches, J., Bellon, A., Bulone, J., Tournier, A., Deygas, O., Herluison, J.-C., Doise, D., Berrebi, E.
Format Journal Article
LanguageEnglish
Published IEEE 01.11.1999
Subjects
Architecture
Cameras
Coders
Computer programs
Costs
Decoding
Displays
Encoders
Hardware
Image coding
ISDN
Microprocessors
Partitioning
Pictures
Software
Software standards
Video codecs
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Summary:A single-chip video codec with embedded display controller for videotelephony applications is described. It encodes and decodes simultaneously up to 30 CIF pictures per second according to video-conferencing recommendations H261, H263 (all five options), and H263+ (six additional options). The die area is 132 mm/sup 2/ in a 0.35-/spl mu/m technology, and the power consumption is 1.4 W. The chip uses a distributed dedicated multiprocessor architecture; where computation-intensive functions are done by dedicated hardware, and where picture quality or standard dependent parts are done in software on dedicated programmable processors. Main architectural choices are discussed, and emphasis is put on hardware/software partitioning and codesign.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
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ISSN:0018-9200
1558-173X
DOI:10.1109/4.799872