Hierarchical algorithm partitioning at system level for an improved utilization of memory structures

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 18; no. 1; pp. 14 - 24
• Main Authors: Eckhardt, U., Merker, R.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.01.1999; Institute of Electrical and Electronics Engineers
• Subjects: Algorithm design and analysis; Algorithms; Applied sciences; Architecture; Arrays; Computer aided design; Costs; Design engineering; Design. Technologies. Operation analysis. Testing; Electronics; Energy consumption; Exact sciences and technology; Integrated circuits; Memory architecture; Parallel processing; Partitioning; Partitioning algorithms; Processor scheduling; Registers; Reuse; Scheduling; Scheduling algorithm; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; System performance; Circuit architecture; Performance evaluation; Partitioning; Memory; Codesign; Integrated circuit; Parallel processing; Hierarchical system; Algorithm; Computer aided design

The object of algorithm design in context with a hierarchically structured memory system is a reduction of access cycles to higher memory levels by an increase of data reuse from levels closer to execution units. The object of our approach is to systematically construct an algorithm coding, starting...