Multi-bits error detection and fast recovery in RISC cores

• Published in: Journal of semiconductors Vol. 36; no. 11; pp. 106 - 113
• Main Author: 王晶 杨星 赵元富 张伟功 申娇 邱柯妮
• Format: Journal Article
• Language: English
• Published: Chinese Institute of Electronics 01.11.2015
• Subjects: automatic recovery; Error detection; Errors; MBU; MBUS; Microprocessors; pipeline hardened; Pipelines; Recovery; RISC; RISC核; RISC结构; Semiconductors; SET; SEU; Soft errors; 多比特; 微处理器; 快速恢复; 特征尺寸; 错误检测
• ISSN: 1674-4926
• DOI: 10.1088/1674-4926/36/11/115009

The particles-induced soft errors are a major threat to the reliability of microprocessors. Even worse,multi-bits upsets（MBUs） are ever-increased due to the rapidly shrinking feature size of the IC on a chip. Several architecture-level mechanisms have been proposed to protect microprocessors from soft errors, such as dual and triple modular redundancies（DMR and TMR）. However, most of them are inefficient to combat the growing multibits errors or cannot well balance the critical paths delay, area and power penalty. This paper proposes a novel architecture, self-recovery dual-pipeline（SRDP）, to effectively provide soft error detection and recovery with low cost for general RISC structures. We focus on the following three aspects. First, an advanced DMR pipeline is devised to detect soft error, especially MBU. Second, SEU/MBU errors can be located by enhancing self-checking logic into pipelines stage registers. Third, a recovery scheme is proposed with a recovery cost of 1 or 5 clock cycles.Our evaluation of a prototype implementation exhibits that the SRDP can successfully detect particle-induced soft errors up to 100% and recovery is nearly 95%, the other 5% will inter a specific trap.