Charge‐sharing read port with bitline pre‐charging and sensing scheme for low‐power SRAMs

• Published in: International journal of circuit theory and applications Vol. 45; no. 9; pp. 1231 - 1248
• Main Authors: Maroof, Naeem, Sohail, Muhammad, Shin, Hyunchul
• Format: Journal Article
• Language: English
• Published: Bognor Regis Wiley Subscription Services, Inc 01.09.2017
• Subjects: charge sharing; Charging; differential read; Electric potential; leakage suppression; low power; Random access memory; sense amplifier; SRAM; Static random access memory; Transistors; write driver
• DOI: 10.1002/cta.2311
• ISSN: 0098-9886

Summary In this paper, we present our decoupled differential read (DDR) port and bitline (BL) pre‐charging scheme. The proposed scheme allows the charge sharing between bitlines during the read operation. DDR port isolates the internal nodes, thus improves the read static noise margin and allows the subthreshold operation. BLs are not pre‐charged to full VDD. Read port is designed such that for the read ‘1’ operation, BL shares its charge with BLB, and for read ‘0’ operation, BL is charged toward VDD and BLB is discharged to the ground. The proposed non‐VDD BL pre‐charging and the charge‐sharing mechanism provide substantial read power savings. Virtual power rail is used to suppress the BL leakages. A dynamic voltage level shifting pre‐amplifier is used that shifts both BLs to the middle voltage and amplifies the voltage difference. Single‐ended write driver is also presented that only conditionally charges the write BL. The proposed 10‐transistor static random access memory cell using DDR provides more than 2 times read static noise margin, ~72% read power savings, and ~40% write power savings compared with the conventional six‐transistor static random access memory. Copyright © 2016 John Wiley & Sons, Ltd. We present our decoupled differential read port and bitline pre‐charging scheme that allows charge‐sharing mechanism between the bitline pair during the read operation. A single‐ended write driver circuit is also presented for low‐power write operation. Read power savings of ~72% and write power savings of ~40% are reported.