Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip
One of the difficult problems facing core-based system-on-chip (SoC) designs is test access. For testing the cores in an SoC, a special mechanism is required since they are not directly accessible via chip inputs and outputs. In this paper, we introduce a novel test access mechanism (TAM) based on t...
Saved in:
| Published in | Integration (Amsterdam) Vol. 40; no. 2; pp. 149 - 160 |
|---|---|
| Main Authors | , , , |
| Format | Journal Article |
| Language | English |
| Published |
Elsevier B.V
01.02.2007
|
| Subjects | |
| Online Access | Get full text |
Cover
Loading…
| Abstract | One of the difficult problems facing core-based system-on-chip (SoC) designs is test access. For testing the cores in an SoC, a special mechanism is required since they are not directly accessible via chip inputs and outputs. In this paper, we introduce a novel test access mechanism (TAM) based on time-division multiplexing (TDM). This so-called TDM-TAM is P1500 compatible and, in fact, uses a P1500 wrapper. The TAM advantages are its flexibility, scalability, and reconfigurability. Also this TAM could be very useful for testing multi-frequency cores in SoCs because, with TDM, the test data rate can be changed. The proposed TAM is compared with two other approaches: a serial threading approach analogous to the IEEE1149.1 standard (Serial TAM) and a packet-switching test network (called NIMA). A network processing unit is used as an SoC platform to compare the different TAMs. Results show that, in most cases, TDM is the most effective TAM in both test time and overhead area. |
|---|---|
| AbstractList | One of the difficult problems facing core-based system-on-chip (SoC) designs is test access. For testing the cores in an SoC, a special mechanism is required since they are not directly accessible via chip inputs and outputs. In this paper, we introduce a novel test access mechanism (TAM) based on time-division multiplexing (TDM). This so-called TDM-TAM is P1500 compatible and, in fact, uses a P1500 wrapper. The TAM advantages are its flexibility, scalability, and reconfigurability. Also this TAM could be very useful for testing multi-frequency cores in SoCs because, with TDM, the test data rate can be changed. The proposed TAM is compared with two other approaches: a serial threading approach analogous to the IEEE1149.1 standard (Serial TAM) and a packet-switching test network (called NIMA). A network processing unit is used as an SoC platform to compare the different TAMs. Results show that, in most cases, TDM is the most effective TAM in both test time and overhead area. |
| Author | Ebadi, Zahra S. Avanaki, Alireza N. Saleh, Resve Ivanov, Andre |
| Author_xml | – sequence: 1 givenname: Zahra S. surname: Ebadi fullname: Ebadi, Zahra S. organization: Department of Electrical and Computer Engineering, University of British Columbia, 2356 Main Mall, Vancouver, BC, Canada V6T 1Z4 – sequence: 2 givenname: Alireza N. surname: Avanaki fullname: Avanaki, Alireza N. organization: Department of Electrical and Computer Engineering, University of Tehran, P.O. Box 14395-515, Tehran, Iran – sequence: 3 givenname: Resve surname: Saleh fullname: Saleh, Resve email: res@ece.ubc.ca organization: Department of Electrical and Computer Engineering, University of British Columbia, 2356 Main Mall, Vancouver, BC, Canada V6T 1Z4 – sequence: 4 givenname: Andre surname: Ivanov fullname: Ivanov, Andre organization: Department of Electrical and Computer Engineering, University of British Columbia, 2356 Main Mall, Vancouver, BC, Canada V6T 1Z4 |
| BookMark | eNp9kD1PwzAQhi1UJErhDzBlYks4203cSCyofEqVWGC2XPvcukrsYKcV_fcklJnpdNLzvrp7LsnEB4-E3FAoKNDqblccmuQKBlAVwAoAdkamdCFYLkrGJmQ6QCKvWQUX5DKlHQDQuSinRD1ichufKW8y13YNtuh71bvgs2CziDp46zb7qNYN_kK2wW83Lj2mPlNaY0pZi3qrvEttZkPM0jH12ObB53rruityblWT8Ppvzsjn89PH8jVfvb-8LR9Wueac9vmiKuclF0LXwGhNuamEplyU2lSUa1OvFWPCKlVChdaurRUgFKsrY0AvTK34jNyeersYvvbDcbJ1SWPTKI9hnySrGfAFZwPITqCOIaWIVnbRtSoeJQU52pQ7OdqUo00JTA42h9D9KYTDCweHUSbt0Gs0bpDUSxPcf_Efa8KBVQ |
| CitedBy_id | crossref_primary_10_1016_j_vlsi_2016_12_011 |
| Cites_doi | 10.1109/TEST.1998.743167 10.1109/TEST.1998.743168 10.1109/ETW.2001.946668 10.1109/VTEST.1997.599435 10.1109/TEST.1998.743146 10.1109/TEST.1990.114058 10.1109/TEST.1997.639596 10.1109/TEST.2000.894302 10.1109/43.806811 10.1109/ATS.2001.990282 10.1109/TEST.1999.805839 10.1007/978-1-4615-0351-4_12 10.1023/A:1014916913577 10.1109/VTEST.2000.843836 |
| ContentType | Journal Article |
| Copyright | 2006 Elsevier B.V. |
| Copyright_xml | – notice: 2006 Elsevier B.V. |
| DBID | AAYXX CITATION 7SP 8FD L7M |
| DOI | 10.1016/j.vlsi.2006.02.002 |
| DatabaseName | CrossRef Electronics & Communications Abstracts Technology Research Database Advanced Technologies Database with Aerospace |
| DatabaseTitle | CrossRef Technology Research Database Advanced Technologies Database with Aerospace Electronics & Communications Abstracts |
| DatabaseTitleList | Technology Research Database |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EISSN | 1872-7522 |
| EndPage | 160 |
| ExternalDocumentID | 10_1016_j_vlsi_2006_02_002 S0167926006000356 |
| GroupedDBID | --K --M -~X .DC .~1 0R~ 1B1 1~. 1~5 29J 4.4 457 4G. 5GY 5VS 7-5 71M 8P~ 9JN AACTN AAEDT AAEDW AAIAV AAIKJ AAKOC AALRI AAOAW AAQFI AAQXK AAXUO AAYFN ABBOA ABFNM ABJNI ABMAC ABXDB ABYKQ ACDAQ ACGFS ACNNM ACRLP ACZNC ADBBV ADEZE ADJOM ADMUD ADTZH AEBSH AECPX AEKER AFKWA AFTJW AGHFR AGUBO AGYEJ AHHHB AHJVU AHZHX AIALX AIEXJ AIKHN AITUG AJBFU AJOXV ALMA_UNASSIGNED_HOLDINGS AMFUW AMRAJ AOUOD ASPBG AVWKF AXJTR AZFZN BJAXD BKOJK BLXMC CS3 EBS EFJIC EFLBG EJD EO8 EO9 EP2 EP3 F0J F5P FDB FEDTE FGOYB FIRID FNPLU FYGXN G-2 G-Q G8K GBLVA GBOLZ HLZ HVGLF HZ~ IHE J1W JJJVA KOM LG9 LY7 M41 MO0 N9A O-L O9- OAUVE OZT P-8 P-9 P2P PC. Q38 R2- RIG ROL RPZ SBC SDF SDG SDP SES SET SEW SPC SPCBC SST SSV SSZ T5K UHS WUQ XPP ZMT ~G- AAXKI AAYXX AFJKZ CITATION 7SP 8FD L7M |
| ID | FETCH-LOGICAL-c331t-86545377c9021913d67c1375cd613cd9ba227faa506effbff707a296dd0c8d9a3 |
| IEDL.DBID | .~1 |
| ISSN | 0167-9260 |
| IngestDate | Fri Oct 25 00:02:40 EDT 2024 Thu Sep 26 19:48:16 EDT 2024 Fri Feb 23 02:22:05 EST 2024 |
| IsPeerReviewed | true |
| IsScholarly | true |
| Issue | 2 |
| Keywords | Optimal test time SoC testing Embedded core testing Time-division multiplexed TAM Test access mechanism |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c331t-86545377c9021913d67c1375cd613cd9ba227faa506effbff707a296dd0c8d9a3 |
| Notes | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
| PQID | 29203832 |
| PQPubID | 23500 |
| PageCount | 12 |
| ParticipantIDs | proquest_miscellaneous_29203832 crossref_primary_10_1016_j_vlsi_2006_02_002 elsevier_sciencedirect_doi_10_1016_j_vlsi_2006_02_002 |
| PublicationCentury | 2000 |
| PublicationDate | 2007-02-01 |
| PublicationDateYYYYMMDD | 2007-02-01 |
| PublicationDate_xml | – month: 02 year: 2007 text: 2007-02-01 day: 01 |
| PublicationDecade | 2000 |
| PublicationTitle | Integration (Amsterdam) |
| PublicationYear | 2007 |
| Publisher | Elsevier B.V |
| Publisher_xml | – name: Elsevier B.V |
| References | L. Hong, M. Nahvi, R. Fung, A. Ivanov, R. Saleh, Novel test methodologies for soc/ip design implementation and comparison, in: Proceedings of the IEEE International Workshop on System-on-Chip for Real-Time Applications, 2002, pp. 20–30. IEEE P1500 web site S. Goel, E. Marinissen, TAM architecture and their implication on test application time, in: Proceedings of the International Workshop on Test Embedded Core-based Systems, 2001, pp. 3.3–1–10. Y. Zorian, E. Marinissen, S. Dey, Testing embedded-core based system chips, in: Proceedings of the International Test Conference, 1998, pp. 130–143. I. Ghosh, N. Jha, S. Dey, A low overhead design for testability and test generation technique for core-based systems, in: Proceedings of the International Test Conference, 1999, pp. 50–59. ITC’02 SoC Test Benchmarks Shanmugam (bib11) 1979 . V. Immaneni, S. Raman, Direct access test scheme-design of block and core cells for embedded asics, in: Proceedings of the International Test Conference, 1990, pp. 488–492. E. Marinissen, A structures and scalable mechanism for test access to embedded reusable cores, in: Proceedings of the International Test Conference, 1998, pp. 284–293. L. Whetsel, Addressable test ports: an approach to testing embedded cores, in: Proceedings of the International Test Conference, 1999, pp. 1055–1064. P. Varma, S. Bhatia, A structured test re-use methodology for core-based system chips, in: Proceedings of the International Test Conference, 1998, pp. 294–302. N. Touba, B. Pouya, Testing embedded cores using partial isolation rings, in: Proceedings of the International Test Conference, 1997, pp. 10–16. K. Chakrabarty, Design of a system-on-chip test access architecture using integer linear programming, in: Proceedings of the VLSI Test Symposium, 2000, pp. 127–134. Iyengar, Chakrabarty, Marinissen (bib18) 2001; 18 M. Nahvi, A. Ivanov, A packet switching communication-based test access mechanism for system chips, in: Proceedings of the European Test Workshop, 2001, pp. 81–86. L. Whetsel, An IEEE 1149.1 based test access architecture for IC with embedded cores, in: Proceedings of the International Test Conference, 1997, pp. 69–78. L. Whetsel, Core test connectivity communication and control, in: Proceedings of the International Test Conference, 1998, pp. 303–312. Z. Ebadi, A. Ivanov, Design of an optimal test access architecture using genetic algorithm, in: Proceedings of the Asian Test Symposium, 2001, pp. 205–210. E. Marinissen, S. Goel, M. Lousberg, Wrapper design for embedded core test, in: Proceedings of the International Test Conference, 2000, pp. 911–920. 10.1016/j.vlsi.2006.02.002_bib16 10.1016/j.vlsi.2006.02.002_bib15 10.1016/j.vlsi.2006.02.002_bib14 10.1016/j.vlsi.2006.02.002_bib13 10.1016/j.vlsi.2006.02.002_bib12 10.1016/j.vlsi.2006.02.002_bib10 Iyengar (10.1016/j.vlsi.2006.02.002_bib18) 2001; 18 10.1016/j.vlsi.2006.02.002_bib4 10.1016/j.vlsi.2006.02.002_bib5 10.1016/j.vlsi.2006.02.002_bib2 10.1016/j.vlsi.2006.02.002_bib3 10.1016/j.vlsi.2006.02.002_bib8 Shanmugam (10.1016/j.vlsi.2006.02.002_bib11) 1979 10.1016/j.vlsi.2006.02.002_bib9 10.1016/j.vlsi.2006.02.002_bib19 10.1016/j.vlsi.2006.02.002_bib6 10.1016/j.vlsi.2006.02.002_bib7 10.1016/j.vlsi.2006.02.002_bib17 10.1016/j.vlsi.2006.02.002_bib1 |
| References_xml | – volume: 18 start-page: 213 year: 2001 end-page: 230 ident: bib18 article-title: Test wrapper and test access mechanism co-optimization for system-on-a-chip publication-title: J. Electron. Testing: Theory Appl. (JETTA) contributor: fullname: Marinissen – year: 1979 ident: bib11 article-title: Digital and Analog Communication Systems contributor: fullname: Shanmugam – ident: 10.1016/j.vlsi.2006.02.002_bib9 doi: 10.1109/TEST.1998.743167 – ident: 10.1016/j.vlsi.2006.02.002_bib6 doi: 10.1109/TEST.1998.743168 – ident: 10.1016/j.vlsi.2006.02.002_bib7 doi: 10.1109/ETW.2001.946668 – year: 1979 ident: 10.1016/j.vlsi.2006.02.002_bib11 contributor: fullname: Shanmugam – ident: 10.1016/j.vlsi.2006.02.002_bib4 doi: 10.1109/VTEST.1997.599435 – ident: 10.1016/j.vlsi.2006.02.002_bib1 doi: 10.1109/TEST.1998.743146 – ident: 10.1016/j.vlsi.2006.02.002_bib2 doi: 10.1109/TEST.1990.114058 – ident: 10.1016/j.vlsi.2006.02.002_bib16 – ident: 10.1016/j.vlsi.2006.02.002_bib5 doi: 10.1109/TEST.1997.639596 – ident: 10.1016/j.vlsi.2006.02.002_bib17 doi: 10.1109/TEST.2000.894302 – ident: 10.1016/j.vlsi.2006.02.002_bib3 doi: 10.1109/43.806811 – ident: 10.1016/j.vlsi.2006.02.002_bib12 – ident: 10.1016/j.vlsi.2006.02.002_bib13 – ident: 10.1016/j.vlsi.2006.02.002_bib15 doi: 10.1109/ATS.2001.990282 – ident: 10.1016/j.vlsi.2006.02.002_bib10 doi: 10.1109/TEST.1999.805839 – ident: 10.1016/j.vlsi.2006.02.002_bib19 doi: 10.1007/978-1-4615-0351-4_12 – ident: 10.1016/j.vlsi.2006.02.002_bib8 – volume: 18 start-page: 213 year: 2001 ident: 10.1016/j.vlsi.2006.02.002_bib18 article-title: Test wrapper and test access mechanism co-optimization for system-on-a-chip publication-title: J. Electron. Testing: Theory Appl. (JETTA) doi: 10.1023/A:1014916913577 contributor: fullname: Iyengar – ident: 10.1016/j.vlsi.2006.02.002_bib14 doi: 10.1109/VTEST.2000.843836 |
| SSID | ssj0001475 |
| Score | 1.7637154 |
| Snippet | One of the difficult problems facing core-based system-on-chip (SoC) designs is test access. For testing the cores in an SoC, a special mechanism is required... |
| SourceID | proquest crossref elsevier |
| SourceType | Aggregation Database Publisher |
| StartPage | 149 |
| SubjectTerms | Embedded core testing Optimal test time SoC testing Test access mechanism Time-division multiplexed TAM |
| Title | Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip |
| URI | https://dx.doi.org/10.1016/j.vlsi.2006.02.002 https://search.proquest.com/docview/29203832 |
| Volume | 40 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwnV05T8MwFLaqssCAOEU5igc2FJo4jhOPVaEqhyoEVOpmOXYMQTSpejDy2_HLwSXEwBQlcqLo2X6Xv_c9hE40U2BZmUOlC9mqhDqcRNKhVEc24jLgMwDaYsgGI3o1DsYN1KtrYQBWWen-UqcX2rp60qmk2ZmmaeceAPQc-NVZcR4GtNtAtmXX9NnbJ8zDo2FQ83vD6KpwpsR4vb7M0-pAgnykVn4xTj_UdGF7-htovXIacbf8r03USLIttPaFSnAbyfMCioFlpnE6qUHhIHWcG1yEvSZ9XM6gUqoYZIAJE26sr7nAsuibiCcJFAKn8wm2viwuWZ6dPHPUUzrdQaP-xUNv4FTtExzl-97CiZj1jvwwVNzace75moXK88NAaWvCleaxJCQ0UtqZSoyJjQndUBLOtHZVpLn0d1Ezy7NkD2EdERpIqhSPPBprEkseexpKS4KYGOa20GktNzEtWTJEDR97FiBlaHfJhEuElXILBbVoxbe5FlaN__necT0Pwm4CONmQWZIv5wJabtlQm-z_88sHaLXM2QJM5RA1F7NlcmSdjUXcLlZTG610e3c3t3C9vB4M3wGTZdW- |
| link.rule.ids | 315,783,787,4511,24130,27938,27939,45599,45693 |
| linkProvider | Elsevier |
| linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwnV07T8MwELZKGYAB8RTlVQ9sKDRxHCceUaEqULrQSt0sx44hiKZVH4z8dnx58BJiYEzkRNGdcw_fd98hdKaZAs_KHCpdOK1KqMNJJB1KdWQzLgMxA6At-qw7pLejYFRD7aoXBmCVpe0vbHpurcs7rVKarWmath4AQM-BX53l9TC2glYp8GfZTX3x9onz8GgYVATfsLzsnClAXq8v87SsSJCPs5VfvNMPO507n84W2iyjRnxZfNg2qiXZDtr4wiW4i-RVjsXAMtM4HVeocBA7nhic570mfVzOoFUqX2SAChMubLC5wDIfnIjHCXQCp_MxtsEsLmienUnmqKd0uoeGnetBu-uU8xMc5fvewomYDY_8MFTcOnLu-ZqFyvPDQGnrw5XmsSQkNFJaVSXGxMaEbigJZ1q7KtJc-vuonk2y5ABhHREaSKoUjzwaaxJLHnsaekuCmBjmNtB5JTcxLWgyRIUfexYgZZh3yYRLhJVyAwWVaMU3ZQtrx_98rlnpQdi_AEobMksmy7mAmVs21yaH_3xzE611B_c90bvp3x2h9eIAFzArx6i-mC2TExt5LOLTfGe9Axxf1cs |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Design+and+implementation+of+reconfigurable+and+flexible+test+access+mechanism+for+system-on-chip&rft.jtitle=Integration+%28Amsterdam%29&rft.au=Ebadi%2C+Zahra+S&rft.au=Avanaki%2C+Alireza+N&rft.au=Saleh%2C+Resve&rft.au=Ivanov%2C+Andre&rft.date=2007-02-01&rft.issn=0167-9260&rft.volume=40&rft.issue=2&rft.spage=149&rft.epage=160&rft_id=info:doi/10.1016%2Fj.vlsi.2006.02.002&rft.externalDBID=NO_FULL_TEXT |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0167-9260&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0167-9260&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0167-9260&client=summon |