CMOS‐Integrated Ternary Content Addressable Memory using Nanocavity CBRAMs for High Sensing Margin

• Published in: Small (Weinheim an der Bergstrasse, Germany) Vol. 20; no. 34; pp. e2310943 - n/a
• Main Authors: Hyun, Gihwan, Alimkhanuly, Batyrbek, Seo, Donguk, Lee, Minwoo, Bae, Junseong, Lee, Seunghyun, Patil, Shubham, Hwang, Youngcheol, Kadyrov, Arman, Yoo, Hyungyu, Devnath, Anupom, Lee, Yoonmyung
• Format: Journal Article
• Language: English
• Published: Germany Wiley Subscription Services, Inc 01.08.2024
• Subjects: anodic aluminum oxide template; Arrays; Associative memory; CMOS; CMOS integration; conductive bridge random‐access memory; memory sensing margin; Static random access memory; ternary content addressable memory; Transistors; anodic aluminum oxide template; memory sensing margin; CMOS integration; ternary content addressable memory; conductive bridge random‐access memory
• DOI: 10.1002/smll.202310943
• ISSN: 1613-6810; 1613-6829

The development of data‐intensive computing methods imposes a significant load on the hardware, requiring progress toward a memory‐centric paradigm. Within this context, ternary content‐addressable memory (TCAM) can become an essential platform for high‐speed in‐memory matching applications of large data vectors. Compared to traditional static random‐access memory (SRAM) designs, TCAM technology using non‐volatile resistive memories (RRAMs) in two‐transistor‐two‐resistor (2T2R) configurations presents a cost‐efficient alternative. However, the limited sensing margin between the match and mismatch states in RRAM structures hinders the potential of using memory‐based TCAMs for large‐scale architectures. Therefore, this study proposes a practical device engineering method to improve the switching response of conductive‐bridge memories (CBRAMs) integrated with existing complementary metal‐oxide‐semiconductor (CMOS) transistor technology. Importantly, this work demonstrates a significant improvement in memory window reaching 1.87 × 107 by incorporating nanocavity arrays and modifying electrode geometry. Consequently, TCAM cells using nanocavity‐enhanced CBRAM devices can exhibit a considerable increase in resistance ratio up to 6.17 × 105, thereby closely approximating the sensing metrics observed in SRAM‐based TCAMs. The improved sensing capability facilitates the parallel querying of extensive data sets. TCAM array simulations using experimentally verified device models indicate a substantial sensing margin of 65× enabling a parallel search of 2048 bits. Although RRAM‐based TCAM offers the advantage of reduced cell area, its constrained sensing margin can notably impede parallel data search functionality. This study demonstrates that incorporating nanocavity arrays into CBRAM technology using AAO nanotemplate and integrating with 180 nm CMOS FETs in 2T2R configuration can significantly enhance the sensing margin characteristics favorable for TCAM applications.