Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 57; no. 12; pp. 3039 - 3047
• Main Authors: Tu, Ming-Hsien, Lin, Jihi-Yu, Tsai, Ming-Chien, Jou, Shyh-Jye, Chuang, Ching-Te
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Asymmetry; Chips; Circuits; CMOS; CMOS technology; Grounds; Low power; Low power electronics; Low voltage; Noise; Power consumption; single-ended SRAM; SRAM chips; Static random access memory

In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemen...