Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemen...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. I, Regular papers Vol. 57; no. 12; pp. 3039 - 3047
Main Authors Tu, Ming-Hsien, Lin, Jihi-Yu, Tsai, Ming-Chien, Jou, Shyh-Jye, Chuang, Ching-Te
Format Journal Article
LanguageEnglish
Published New York IEEE 01.12.2010
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Asymmetry
Chips
Circuits
CMOS
CMOS technology
Grounds
Low power
Low power electronics
Low voltage
Noise
Power consumption
single-ended SRAM
SRAM chips
Static random access memory
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Summary:In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V V DD , an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 μW.
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2010.2071690