High-speed noise-immune AlGaAs/GaAs HBT logic for static memory application
The authors evaluate the performance of a new gate topology that gives large logic swings and a high noise margin at low power dissipation. The measured noise margin (43% of the 3-V logic swing) and transfer characteristics for a hybrid inverter using an AlGaAs/GaAs heterojunction bipolar transistor...
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Published in | IEEE transactions on electron devices Vol. 38; no. 4; pp. 932 - 934 |
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Main Authors | , , , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.04.1991
Institute of Electrical and Electronics Engineers |
Subjects | |
Online Access | Get full text |
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Summary: | The authors evaluate the performance of a new gate topology that gives large logic swings and a high noise margin at low power dissipation. The measured noise margin (43% of the 3-V logic swing) and transfer characteristics for a hybrid inverter using an AlGaAs/GaAs heterojunction bipolar transistor (HBT) are presented along with simulated data for an integrated device. These simulations lead to a modified structure demonstrating substantially improved transient response and reduced power dissipation (23 ps and 2.1 mW) while maintaining a large noise margin (45% of the 3-V logic swing). Its performance compares favorably with that of emitter coupled logic (ECL).< > |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0018-9383 1557-9646 |
DOI: | 10.1109/16.75227 |