Characterization of Single Bit and Multiple Cell Soft Error Events in Planar and FinFET SRAMs
We characterize soft errors of SRAM devices fabricated over a range of technology nodes and show that both single-bit upsets (SBUs) and multiple-cell upsets (MCUs) decrease with technology scaling. Implementation of FinFET transistors leads to a significant reduction in both SBUs and MCUs relative t...
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Published in | IEEE transactions on device and materials reliability Vol. 16; no. 2; pp. 132 - 137 |
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Main Authors | , |
Format | Magazine Article |
Language | English |
Published |
New York
IEEE
01.06.2016
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
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Abstract | We characterize soft errors of SRAM devices fabricated over a range of technology nodes and show that both single-bit upsets (SBUs) and multiple-cell upsets (MCUs) decrease with technology scaling. Implementation of FinFET transistors leads to a significant reduction in both SBUs and MCUs relative to planar transistors. We find the mechanisms responsible for SBU and MCU events are unaffected by the transition to the FinFET architecture. For errors due to alpha particles and thermal neutrons, the relative occurrence of single event upsets is determined primarily by the sensitive area of the drain of bit cell transistors. We show that high-energy neutron-induced MCU events are determined by charge sharing among adjacent cells and are sensitive to both transistor drain area and the details of the process technology (i.e., manufacturing sequence) used, via the dependence of charge mobility on the substrate doping level. |
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AbstractList | We characterize soft errors of SRAM devices fabricated over a range of technology nodes and show that both single-bit upsets (SBUs) and multiple-cell upsets (MCUs) decrease with technology scaling. Implementation of FinFET transistors leads to a significant reduction in both SBUs and MCUs relative to planar transistors. We find the mechanisms responsible for SBU and MCU events are unaffected by the transition to the FinFET architecture. For errors due to alpha particles and thermal neutrons, the relative occurrence of single event upsets is determined primarily by the sensitive area of the drain of bit cell transistors. We show that high-energy neutron-induced MCU events are determined by charge sharing among adjacent cells and are sensitive to both transistor drain area and the details of the process technology (i.e., manufacturing sequence) used, via the dependence of charge mobility on the substrate doping level. |
Author | Yi-Pin Fang Oates, Anthony S. |
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Cites_doi | 10.1109/TDMR.2008.2000892 10.1109/T-ED.1979.19370 10.1587/transfun.E96.A.1579 10.1109/23.903813 10.1109/JSSC.2004.826321 10.1109/RELPHY.2006.251220 10.1109/TNS.2012.2218128 10.1109/16.543043 10.1109/TNS.2007.908147 10.1109/TDMR.2013.2287699 10.1109/CICC.2006.321010 10.1109/TDMR.2011.2168959 10.1149/1.3056376 10.1109/55.20423 10.1109/TED.2010.2047907 10.1109/TNS.2006.884788 10.1109/TNS.2009.2015312 10.1109/T-ED.1983.21207 10.1109/RAMS.2011.5754515 10.1063/1.367067 10.1109/RELPHY.2000.843906 10.1109/JPROC.2002.808156 10.1126/science.206.4420.776 10.1109/IIRW.2010.5706480 |
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Keywords | alpha particles Single event upsets (SEU) multiple-cell upsets (MCU) soft error rate (SER) FinFET high-energy neutrons SRAM thermal neutrons single-bit upsets (SBU) |
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Snippet | We characterize soft errors of SRAM devices fabricated over a range of technology nodes and show that both single-bit upsets (SBUs) and multiple-cell upsets... |
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SubjectTerms | Alpha particles Charge Computer architecture Devices Drains FinFET FinFETs high-energy neutrons Materials reliability multiple-cell upsets (MCU) Neutrons Random access memory Semiconductor devices Single event upsets single event upsets (SEU) single-bit upsets (SBU) soft error rate (SER) Soft errors SRAM Thermal neutrons Transistors |
Title | Characterization of Single Bit and Multiple Cell Soft Error Events in Planar and FinFET SRAMs |
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