Characterization of Single Bit and Multiple Cell Soft Error Events in Planar and FinFET SRAMs

• Published in: IEEE transactions on device and materials reliability Vol. 16; no. 2; pp. 132 - 137
• Main Authors: Yi-Pin Fang, Oates, Anthony S.
• Format: Magazine Article
• Language: English
• Published: New York IEEE 01.06.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Alpha particles; Charge; Computer architecture; Devices; Drains; FinFET; FinFETs; high-energy neutrons; Materials reliability; multiple-cell upsets (MCU); Neutrons; Random access memory; Semiconductor devices; Single event upsets; single event upsets (SEU); single-bit upsets (SBU); soft error rate (SER); Soft errors; SRAM; Thermal neutrons; Transistors; alpha particles; Single event upsets (SEU); multiple-cell upsets (MCU); soft error rate (SER); FinFET; high-energy neutrons; SRAM; thermal neutrons; single-bit upsets (SBU)
• DOI: 10.1109/TDMR.2016.2535663
• ISSN: 1530-4388

We characterize soft errors of SRAM devices fabricated over a range of technology nodes and show that both single-bit upsets (SBUs) and multiple-cell upsets (MCUs) decrease with technology scaling. Implementation of FinFET transistors leads to a significant reduction in both SBUs and MCUs relative to planar transistors. We find the mechanisms responsible for SBU and MCU events are unaffected by the transition to the FinFET architecture. For errors due to alpha particles and thermal neutrons, the relative occurrence of single event upsets is determined primarily by the sensitive area of the drain of bit cell transistors. We show that high-energy neutron-induced MCU events are determined by charge sharing among adjacent cells and are sensitive to both transistor drain area and the details of the process technology (i.e., manufacturing sequence) used, via the dependence of charge mobility on the substrate doping level.