A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 60; no. 3; pp. 570 - 581
• Main Authors: Lin, Ying-Zu, Liu, Chun-Cheng, Huang, Guan-Ying, Shyu, Ya-Ting, Liu, Yen-Ting, Chang, Soon-Jyh
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2013; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accuracy; Architecture; Ash; Capacitance; Capacitors; Consumption; Control equipment; Electric potential; Flash ADC; hybrid ADC; Logic gates; Nonlinearity; Sampling; SAR ADC; Studies; subrange ADC; Switches; Synthetic aperture radar; Transistors; two-step ADC
• DOI: 10.1109/TCSI.2012.2215756
• ISSN: 1549-8328

This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a differential segmented capacitive digital-to-analog converter (DAC). The flash ADC controls the thermometer coarse capacitors of the DAC and the SAR ADC controls the binary fine ones. Both theoretical analysis and behavioral simulations show that the differential non-linearity (DNL) of a SAR ADC with a segmented DAC is better than that of a binary ADC. The merged switching of the coarse capacitors significantly enhances overall operation speed. At 150 MS/s, the ADC consumes 1.53 mW from a 1.2-V supply. The effective number of bits (ENOB) is 8.69 bits and the effective resolution bandwidth (ERBW) is 100 MHz. With a 1.3-V supply voltage, the sampling rate is 200 MS/s with 2.2-mW power consumption. The ENOB is 8.66 bits and the ERBW is 100 MHz. The FOMs at 1.3 V and 200 MS/s, 1.2 V and 150 MS/s and 1 V and 100 MS/s are 27.2, 24.7, and 17.7 fJ/conversion-step, respectively.