An ASIC chip with pipeline ADCs for CCD sensor imaging system

•Designing a specific integrated circuit is used to TDI CCD imaging system.•Designing a high-resolution and high-throughput pipeline ADC with ASIC.•Analyzing some non-ideal factors for ADC designing.•Achieving a high SNR CCD imaging system. This paper introduces the design of an application specific...

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Published inSensors and actuators. A. Physical. Vol. 279; pp. 284 - 292
Main Authors Sun, Zhenya, Zhang, Da, Fang, Wei
Format Journal Article
LanguageEnglish
Published Lausanne Elsevier B.V 15.08.2018
Elsevier BV
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Abstract •Designing a specific integrated circuit is used to TDI CCD imaging system.•Designing a high-resolution and high-throughput pipeline ADC with ASIC.•Analyzing some non-ideal factors for ADC designing.•Achieving a high SNR CCD imaging system. This paper introduces the design of an application specific integrated circuit (ASIC). It will conduct the image processing for photoelectric image sensor charge coupled device (CCD). The ASIC can convert the analog signal of CCD into a suitable digital signal, which is used as the input for the next stage. To realize the ASIC, a two-channel analog to digital converter (ADC) with the speed of 40 MS/s-100 MS/s and a low voltage differential signaling (LVDS) has been proposed. In the ASIC, the correlated double sampling (CDS) has been integrated into the programmable gain amplifier (PGA). A novel CDS circuit is employed to reduce the amplifier gain error. The unique design reduces the size of ASIC by sharing the same operational amplifier (OPA) block. In the low sampling rate of 40 MHz, the spurious-free dynamic range (SFDR) is larger than 91 dB, and the signal-to-noise-ratio (SNR) is more than 79 dB. In the high sampling rate of 100 MHz, the ADC achieved a high SFDR of 92.2 dB and SNR of 81.47 dB. With a 0.13-μm 1P-6M CMOS process, the ASIC only occupies on the die with a size of 21.16 mm2. With the power supply of 3.3 V and 1.8 V, the power consumption is as low as 405 mW. By using the ASIC with the specially designed ADC, the saturated output image reaches a high SNR of 52.2 dB.
AbstractList •Designing a specific integrated circuit is used to TDI CCD imaging system.•Designing a high-resolution and high-throughput pipeline ADC with ASIC.•Analyzing some non-ideal factors for ADC designing.•Achieving a high SNR CCD imaging system. This paper introduces the design of an application specific integrated circuit (ASIC). It will conduct the image processing for photoelectric image sensor charge coupled device (CCD). The ASIC can convert the analog signal of CCD into a suitable digital signal, which is used as the input for the next stage. To realize the ASIC, a two-channel analog to digital converter (ADC) with the speed of 40 MS/s-100 MS/s and a low voltage differential signaling (LVDS) has been proposed. In the ASIC, the correlated double sampling (CDS) has been integrated into the programmable gain amplifier (PGA). A novel CDS circuit is employed to reduce the amplifier gain error. The unique design reduces the size of ASIC by sharing the same operational amplifier (OPA) block. In the low sampling rate of 40 MHz, the spurious-free dynamic range (SFDR) is larger than 91 dB, and the signal-to-noise-ratio (SNR) is more than 79 dB. In the high sampling rate of 100 MHz, the ADC achieved a high SFDR of 92.2 dB and SNR of 81.47 dB. With a 0.13-μm 1P-6M CMOS process, the ASIC only occupies on the die with a size of 21.16 mm2. With the power supply of 3.3 V and 1.8 V, the power consumption is as low as 405 mW. By using the ASIC with the specially designed ADC, the saturated output image reaches a high SNR of 52.2 dB.
This paper introduces the design of an application specific integrated circuit (ASIC). It will conduct the image processing for photoelectric image sensor charge coupled device (CCD). The ASIC can convert the analog signal of CCD into a suitable digital signal, which is used as the input for the next stage. To realize the ASIC, a two-channel analog to digital converter (ADC) with the speed of 40 MS/s-100 MS/s and a low voltage differential signaling (LVDS) has been proposed. In the ASIC, the correlated double sampling (CDS) has been integrated into the programmable gain amplifier (PGA). A novel CDS circuit is employed to reduce the amplifier gain error. The unique design reduces the size of ASIC by sharing the same operational amplifier (OPA) block. In the low sampling rate of 40 MHz, the spurious-free dynamic range (SFDR) is larger than 91 dB, and the signal-to-noise-ratio (SNR) is more than 79 dB. In the high sampling rate of 100 MHz, the ADC achieved a high SFDR of 92.2 dB and SNR of 81.47 dB. With a 0.13-μm 1P-6M CMOS process, the ASIC only occupies on the die with a size of 21.16 mm2. With the power supply of 3.3 V and 1.8 V, the power consumption is as low as 405 mW. By using the ASIC
Author Sun, Zhenya
Zhang, Da
Fang, Wei
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  surname: Sun
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  givenname: Wei
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  email: Fangw@ciomp.ac.cn
  organization: Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences, Changchun 130033, China
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Snippet •Designing a specific integrated circuit is used to TDI CCD imaging system.•Designing a high-resolution and high-throughput pipeline ADC with ASIC.•Analyzing...
This paper introduces the design of an application specific integrated circuit (ASIC). It will conduct the image processing for photoelectric image sensor...
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SubjectTerms ADC
Amplification
Analog to digital conversion
Analog to digital converters
Application specific integrated circuits
ASIC
CCD
CDS
Charge coupled devices
Circuit design
Circuits
CMOS
Electricity
Gain
Image processing
Integrated circuits
Low voltage
Noise levels
Operational amplifiers
Photoelectric sensor
Photoelectricity
Power consumption
Power supplies
Sampling
Sensors
Title An ASIC chip with pipeline ADCs for CCD sensor imaging system
URI https://dx.doi.org/10.1016/j.sna.2018.06.014
https://www.proquest.com/docview/2116404893
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