Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs
Excessive supply voltage drops in a circuit may lead to significant circuit performance degradation and even malfunction. To handle this problem, existing power delivery aware placement algorithms model voltage drops as an optimization objective. We observe that directly minimizing the voltage drops...
Saved in:
Published in | IEEE transactions on computer-aided design of integrated circuits and systems Vol. 30; no. 11; pp. 1649 - 1662 |
---|---|
Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
New York
IEEE
01.11.2011
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | Excessive supply voltage drops in a circuit may lead to significant circuit performance degradation and even malfunction. To handle this problem, existing power delivery aware placement algorithms model voltage drops as an optimization objective. We observe that directly minimizing the voltage drops in the objective function might not resolve voltage-drop violations effectively and might cause problems in power-integrity convergence. To remedy this deficiency, in this paper, we propose new techniques to incorporate device power spreading forces into a mixed-size analytical placement framework. Unlike the state-of-the-art previous work that handles the worst voltage-drop spots one by one, our approach simultaneously and globally spreads all the blocks with voltage-drop violations to desired locations directly to minimize the violations. To apply the power force, we model macro current density and power rails for our placement framework to derive desired macro/cell locations. To further improve the solution quality, we propose an efficient mathematical transformation to adjust the power force direction and magnitude. Experimental results show that our approach can substantially improve the voltage drops, wirelength, and runtime over the previous work. |
---|---|
AbstractList | Excessive supply voltage drops in a circuit may lead to significant circuit performance degradation and even malfunction. To handle this problem, existing power delivery aware placement algorithms model voltage drops as an optimization objective. We observe that directly minimizing the voltage drops in the objective function might not resolve voltage-drop violations effectively and might cause problems in power-integrity convergence. To remedy this deficiency, in this paper, we propose new techniques to incorporate device power spreading forces into a mixed-size analytical placement framework. Unlike the state-of-the-art previous work that handles the worst voltage-drop spots one by one, our approach simultaneously and globally spreads all the blocks with voltage-drop violations to desired locations directly to minimize the violations. To apply the power force, we model macro current density and power rails for our placement framework to derive desired macro/cell locations. To further improve the solution quality, we propose an efficient mathematical transformation to adjust the power force direction and magnitude. Experimental results show that our approach can substantially improve the voltage drops, wirelength, and runtime over the previous work. |
Author | Yi-Lin Chuang Po-Wei Lee Yao-Wen Chang |
Author_xml | – sequence: 1 givenname: Yi-Lin surname: Chuang fullname: Chuang, Yi-Lin – sequence: 2 givenname: Po-Wei surname: Lee fullname: Lee, Po-Wei – sequence: 3 givenname: Yao-Wen surname: Chang fullname: Chang, Yao-Wen |
BookMark | eNpdkE1rGzEURUVIoU7aH1CyEVllM66eNPpaGjtNAyktJO1WlaVnozAeOdKYxP31HeOQRVYPLudeeOeMnPa5R0K-AJsCMPv1YT5bTDkDmHJQgmk4IROwQjctSDglE8a1aRjT7CM5q_WRMWgltxPy90_uBr_GZlHyls6efUE66323H1LwHf3V-YAb7Ae63NObLi8PWX7GQu-3BX1M_ZqucqE_0gvG5j79QzpPJezSQBdY07qvn8iHle8qfn695-T3t-uH-ffm7ufN7Xx21wTB5dB4ZrQ1reJBe8Ujt5LLVkVtozRecO9jDFxpoW2ISo90y4xBI0WUy6CkEefk6ri7Lflph3Vwm1QDdp3vMe-qA6VBgB2HR_TyHfqYd2V8ujpjjRHccDZCcIRCybUWXLltSRtf9g6YOyh3B-XuoNy9Kh87F8dOQsQ3XrFWgVLiPyTtfMo |
CODEN | ITCSDI |
CitedBy_id | crossref_primary_10_1002_cta_2178 crossref_primary_10_26782_jmcms_2020_07_00016 |
Cites_doi | 10.1109/TCAD.2007.892336 10.1109/DAC.2003.1218834 10.1109/TCAD.2005.846366 10.1145/775832.775860 10.1109/TCAD.2005.844088 10.1145/1687399.1687523 10.1109/ISQED.2007.121 10.1145/309847.310054 10.1109/TCAD.2008.923063 10.1109/ICCD.2005.101 10.1145/378239.379021 |
ContentType | Journal Article |
Copyright | Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Nov 2011 |
Copyright_xml | – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Nov 2011 |
DBID | 97E RIA RIE AAYXX CITATION 7SC 7SP 8FD JQ2 L7M L~C L~D F28 FR3 |
DOI | 10.1109/TCAD.2011.2163071 |
DatabaseName | IEEE All-Society Periodicals Package (ASPP) 2005-present IEEE All-Society Periodicals Package (ASPP) 1998-Present IEL CrossRef Computer and Information Systems Abstracts Electronics & Communications Abstracts Technology Research Database ProQuest Computer Science Collection Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Academic Computer and Information Systems Abstracts Professional ANTE: Abstracts in New Technology & Engineering Engineering Research Database |
DatabaseTitle | CrossRef Technology Research Database Computer and Information Systems Abstracts – Academic Electronics & Communications Abstracts ProQuest Computer Science Collection Computer and Information Systems Abstracts Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Professional Engineering Research Database ANTE: Abstracts in New Technology & Engineering |
DatabaseTitleList | Technology Research Database Technology Research Database |
Database_xml | – sequence: 1 dbid: RIE name: IEL url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/ sourceTypes: Publisher |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Engineering |
EISSN | 1937-4151 |
EndPage | 1662 |
ExternalDocumentID | 2488599071 10_1109_TCAD_2011_2163071 6046166 |
Genre | orig-research |
GroupedDBID | --Z -~X 0R~ 29I 4.4 5GY 5VS 6IK 97E AAJGR AASAJ ABQJQ ABVLG ACGFS ACIWK ACNCT AENEX AETIX AI. AIBXA AKJIK ALLEH ALMA_UNASSIGNED_HOLDINGS ASUFR ATWAV BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 DU5 EBS EJD HZ~ H~9 IBMZZ ICLAB IFIPE IFJZH IPLJI JAVBF LAI M43 O9- OCL P2P PZZ RIA RIE RIG RNS TN5 VH1 VJK XFK AAYXX CITATION 7SC 7SP 8FD JQ2 L7M L~C L~D F28 FR3 |
ID | FETCH-LOGICAL-c325t-a08798462c7a62d2952546d79d58a32aaddc267379cd67a084088e853d5bc6583 |
IEDL.DBID | RIE |
ISSN | 0278-0070 |
IngestDate | Fri Aug 16 10:22:24 EDT 2024 Fri Sep 13 00:45:36 EDT 2024 Fri Aug 23 02:53:55 EDT 2024 Wed Jun 26 19:20:08 EDT 2024 |
IsPeerReviewed | true |
IsScholarly | true |
Issue | 11 |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-LOGICAL-c325t-a08798462c7a62d2952546d79d58a32aaddc267379cd67a084088e853d5bc6583 |
Notes | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
PQID | 898832820 |
PQPubID | 85470 |
PageCount | 14 |
ParticipantIDs | ieee_primary_6046166 proquest_miscellaneous_1671319295 proquest_journals_898832820 crossref_primary_10_1109_TCAD_2011_2163071 |
PublicationCentury | 2000 |
PublicationDate | 2011-Nov. 2011-11-00 20111101 |
PublicationDateYYYYMMDD | 2011-11-01 |
PublicationDate_xml | – month: 11 year: 2011 text: 2011-Nov. |
PublicationDecade | 2010 |
PublicationPlace | New York |
PublicationPlace_xml | – name: New York |
PublicationTitle | IEEE transactions on computer-aided design of integrated circuits and systems |
PublicationTitleAbbrev | TCAD |
PublicationYear | 2011 |
Publisher | IEEE The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher_xml | – name: IEEE – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
References | ref12 ref23 (ref14) 2001 golub (ref8) 1996 ref11 ref10 litovski (ref13) 1997 schewchuk (ref18) 1994 chen (ref15) 2011 ref17 wang (ref20) 2008 ref19 (ref16) 0 (ref1) 0 ref7 wu (ref22) 2004 bhooshan (ref2) 2007 ref9 wein (ref21) 2004 ref4 ref6 ref5 chi (ref3) 2005 |
References_xml | – ident: ref12 doi: 10.1109/TCAD.2007.892336 – ident: ref11 doi: 10.1109/DAC.2003.1218834 – year: 0 ident: ref1 publication-title: ISPD 2006 Placement Contest – year: 2011 ident: ref15 publication-title: NTUplace A VLSI Placement Tool contributor: fullname: chen – ident: ref10 doi: 10.1109/TCAD.2005.846366 – year: 2001 ident: ref14 publication-title: Non-Linear Optimization System and Method for Wire Length and Delay Optimization for an Automatic Electric Circuit Placer – year: 0 ident: ref16 publication-title: Nangate 45 nm Open Cell Library – start-page: 159 year: 2005 ident: ref3 article-title: An IR drop-driven placer for standard cells in a SoC design publication-title: Proc SOC Conf contributor: fullname: chi – start-page: 177 year: 2004 ident: ref22 article-title: Efficient powerground network analysis for power integrity driven design methodology publication-title: Proc ACM/IEEE Des Autom Conf contributor: fullname: wu – ident: ref17 doi: 10.1145/775832.775860 – ident: ref4 doi: 10.1109/TCAD.2005.844088 – start-page: 617 year: 2008 ident: ref20 article-title: Heuristic power/ground network and floorplan co-design method publication-title: Proc IEEE/ACM Asia South Pacific Des Autom Conf contributor: fullname: wang – ident: ref6 doi: 10.1145/1687399.1687523 – year: 1996 ident: ref8 publication-title: Matrix Computations contributor: fullname: golub – ident: ref7 doi: 10.1109/ISQED.2007.121 – start-page: 287 year: 2007 ident: ref2 article-title: Novel and efficient IR-drop models for designing power distribution network for sub-100 nm integrated circuits publication-title: Proc Symp Quality Electron Des contributor: fullname: bhooshan – ident: ref23 doi: 10.1145/309847.310054 – year: 1994 ident: ref18 publication-title: An Introduction to the Conjugate Gradient Method Without the Agonizing Pain contributor: fullname: schewchuk – ident: ref5 doi: 10.1109/TCAD.2008.923063 – year: 2004 ident: ref21 article-title: Hard macros will revolutionize SoC design publication-title: EE Times Online contributor: fullname: wein – year: 1997 ident: ref13 publication-title: VLSI Circuit Simulation and Optimization contributor: fullname: litovski – ident: ref9 doi: 10.1109/ICCD.2005.101 – ident: ref19 doi: 10.1145/378239.379021 |
SSID | ssj0014529 |
Score | 2.040274 |
Snippet | Excessive supply voltage drops in a circuit may lead to significant circuit performance degradation and even malfunction. To handle this problem, existing... |
SourceID | proquest crossref ieee |
SourceType | Aggregation Database Publisher |
StartPage | 1649 |
SubjectTerms | Analytical models Circuit design Design for quality Electric potential Handles Integrated circuit modeling Layout Mathematical analysis Mathematical model Mathematical models Optimization physical design Placement power Spreading Studies Violations Voltage control Voltage drop |
Title | Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs |
URI | https://ieeexplore.ieee.org/document/6046166 https://www.proquest.com/docview/898832820/abstract/ https://search.proquest.com/docview/1671319295 |
Volume | 30 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1bS8MwFD6oT_rgXaxTieCTmNlm6yWPMh1DmAjbxLeaJikMZR1di7pf70naDW8PvhUSQpqTnHw5l-8AnKehpyImI5oqzmnblx7laSSp4ixCdOIqZRNp-_dBb9S-e_KfVuBymQujtbbBZ7ppPq0vX2WyNKayq8CwgwfBKqziOFWu1tJjYByI1p5iGGNxH9ceTM_lV0P8qYqskyH6cEPv2x1ki6r80sT2euluQX8xsSqq5KVZFklTzn9wNv535tuwWeNMcl1tjB1Y0ZNd2PjCPrgHz4_Za4HqhN7k2ZRcv4lcE8tRYs3b5MEY2M2wJPkgVWkA8mBqqpHBNK9C7wkiXtIfv2tFB-O5Jp1xLstxQW5sWMhsH0bd22GnR-uCC1S2mF9Q4UYhR0DCZCgCphj3DVu-CrnyI9FiAnWhZKawDZcqCLF3G3WUxgtf-YlEKNM6gLVJNtGHQBDVKS_1JQJ4k9yVCiG9RHAhpdJMBW0HLhYiiKcVr0Zs3yMuj428YiOvuJaXA3tmSZcd69V0oLEQWlyfvFkc8QiVFOIaB86WrXhkjB9ETHRWzmIvwJc5IlvuH_09cAPWrenYphwew1qRl_oEsUeRnNpN9wlUStTl |
link.rule.ids | 315,786,790,802,27957,27958,55109 |
linkProvider | IEEE |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3NT9swFH8CdgAOsA3QSsfwpJ0QLonbfPhYtaACLUKiIG7GsR2pYmqqNBFb__o9O2kFbIfdIsWynDz7vZ_fx-8B_EgjX8dMxTTVnNNOoHzK01hRzVmM6MTT2hXSjm7CwX3n6jF4XIPTVS2MMcYln5mWfXSxfJ2p0rrKzkLLDh6G6_AB7bzHq2qtVczAhhCdR8VyxuJOrmOYOPBsjJ9V0XUyxB9e5L-xQq6tyl-62BmYi10YLZdW5ZU8t8oiaanFO9bG_137R9ipkSbpVlvjE6yZ6WfYfsU_uAdPD9nPAhUK7efZjHRfZG6IYylxDm5ya13sdlqS_CZVcwBya7uqkbtZXiXfE8S8ZDT5ZTS9mywM6U1yVU4K0neJIfN9uL84H_cGtG65QFWbBQWVXhxxhCRMRTJkmvHA8uXriOsglm0mURsqZlvbcKXDCEd3UEsZNPk6SBSCmfYBbEyzqfkCBHGd9tNAIYS35V2plMpPJJdKacN02GnAyVIEYlYxawh3I_G4sPISVl6illcD9uwvXQ2s_2YDmkuhifrszUXMY1RTiGwa8H31Fg-NjYTIqcnKufBDvJsjtuXB4b8nPobNwXg0FMPLm-smbDlHsitA_AobRV6aI0QiRfLNbcA_u2DYOw |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Voltage-Drop+Aware+Analytical+Placement+by+Global+Power+Spreading+for+Mixed-Size+Circuit+Designs&rft.jtitle=IEEE+transactions+on+computer-aided+design+of+integrated+circuits+and+systems&rft.au=Yi-Lin+Chuang&rft.au=Po-Wei+Lee&rft.au=Yao-Wen+Chang&rft.date=2011-11-01&rft.pub=IEEE&rft.issn=0278-0070&rft.eissn=1937-4151&rft.volume=30&rft.issue=11&rft.spage=1649&rft.epage=1662&rft_id=info:doi/10.1109%2FTCAD.2011.2163071&rft.externalDocID=6046166 |
thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0278-0070&client=summon |
thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0278-0070&client=summon |
thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0278-0070&client=summon |