Design and Analysis of Dual Source Vertical Tunnel Field Effect Transistor for High Performance
An optimally designed Dual Source Vertical Tunnel Field Effect Transistors is proposed and investigated using technology computer aided design simulation. The vertical tunnel FET have dispersal of source channel drain in the vertical direction which will enhance the scalability of the simulated devi...
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| Published in | Transactions on electrical and electronic materials Vol. 21; no. 1; pp. 74 - 82 |
|---|---|
| Main Authors | , , , |
| Format | Journal Article |
| Language | English |
| Published |
Seoul
The Korean Institute of Electrical and Electronic Material Engineers (KIEEME)
01.02.2020
한국전기전자재료학회 |
| Subjects | |
| Online Access | Get full text |
| ISSN | 1229-7607 2092-7592 |
| DOI | 10.1007/s42341-019-00154-2 |
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| Abstract | An optimally designed Dual Source Vertical Tunnel Field Effect Transistors is proposed and investigated using technology computer aided design simulation. The vertical tunnel FET have dispersal of source channel drain in the vertical direction which will enhance the scalability of the simulated device. The benefit of the TFET is switching mechanism which is done by quantum tunnelling method through a barrier instead of thermionic emission over the barrier as that of conventional MOSFETs. The key of this paper, we have developed two-dimensional model of single drain with dual source n-type vertical tunnel field effect transistor. Further introduction to an ultra-thin channel among the drain and gate region will makes aggressive improvement in the numerical simulations of minimum threshold voltage (V
T
) of 0.15 V and average subthreshold slope of 3.47 mV/decade. The variation effect in the channel thickness, source height, drain doping, source doping, temperature and work function has been simulated and examined by 2D silvaco TCAD tool. High ON current and low OFF current is recorded as 1.74 × 10
−4
A/µm and 6.92 × 10
−13
A/µm respectively with I
ON
/I
OFF
current ratio in order of 10
8
to 10
9
. |
|---|---|
| AbstractList | An optimally designed Dual Source Vertical Tunnel Field Effect Transistors is proposed and investigated using technology computer aided design simulation. The vertical tunnel FET have dispersal of source channel drain in the vertical direction which will enhance the scalability of the simulated device. The benefit of the TFET is switching mechanism which is done by quantum tunnelling method through a barrier instead of thermionic emission over the barrier as that of conventional MOSFETs. The key of this paper, we have developed two-dimensional model of single drain with dual source n-type vertical tunnel field effect transistor. Further introduction to an ultra-thin channel among the drain and gate region will makes aggressive improvement in the numerical simulations of minimum threshold voltage (V
T
) of 0.15 V and average subthreshold slope of 3.47 mV/decade. The variation effect in the channel thickness, source height, drain doping, source doping, temperature and work function has been simulated and examined by 2D silvaco TCAD tool. High ON current and low OFF current is recorded as 1.74 × 10
−4
A/µm and 6.92 × 10
−13
A/µm respectively with I
ON
/I
OFF
current ratio in order of 10
8
to 10
9
. An optimally designed Dual Source Vertical Tunnel Field Effect Transistors is proposed and investigated using technology computer aided design simulation. The vertical tunnel FET have dispersal of source channel drain in the vertical direction which will enhance the scalability of the simulated device. The benefit of the TFET is switching mechanism which is done by quantum tunnelling method through a barrier instead of thermionic emission over the barrier as that of conventional MOSFETs. The key of this paper, we have developed two-dimensional model of single drain with dual source n-type vertical tunnel field eff ect transistor. Further introduction to an ultra-thin channel among the drain and gate region will makes aggressiveimprovement in the numerical simulations of minimum threshold voltage (V T ) of 0.15 V and average subthreshold slope of 3.47 mV/decade. The variation effect in the channel thickness, source height, drain doping, source doping, temperature and work function has been simulated and examined by 2D silvaco TCAD tool. High ON current and low OFF current is recorded as 1.74 × 10 −4 A/μm and 6.92 × 10 −13 A/μm respectively with I ON /I OFF current ratio in order of 10 8 to 10 9 . KCI Citation Count: 3 |
| Author | Badgujjar, Soniya Raj, Balwinder Wadhwa, Girish Singh, Shailendra |
| Author_xml | – sequence: 1 givenname: Soniya surname: Badgujjar fullname: Badgujjar, Soniya organization: Nano Electronics Research Lab, Department of Electronics and Communication Engineering, NIT Jalandhar – sequence: 2 givenname: Girish orcidid: 0000-0002-8031-3036 surname: Wadhwa fullname: Wadhwa, Girish email: girishw.17.phd@nitj.ac.in organization: Nano Electronics Research Lab, Department of Electronics and Communication Engineering, NIT Jalandhar – sequence: 3 givenname: Shailendra surname: Singh fullname: Singh, Shailendra organization: Nano Electronics Research Lab, Department of Electronics and Communication Engineering, NIT Jalandhar – sequence: 4 givenname: Balwinder surname: Raj fullname: Raj, Balwinder organization: Nano Electronics Research Lab, Department of Electronics and Communication Engineering, NIT Jalandhar |
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| Cites_doi | 10.1109/TED.2009.2030831 10.1515/aot-2015-0036 10.1109/TED.2005.846318 10.1109/TED.2011.2175228 10.1145/957717.957757 10.1049/mnl.2015.0526 10.1109/LED.2007.892366 10.1109/TED.2016.2539209 10.1109/16.19942 10.1088/1674-4926/37/9/094003 10.1109/16.19963 10.1109/TNANO.2015.2501829 10.1109/TED.2018.2831688 10.1109/TED.2003.821575 10.1016/0003-9861(63)90175-9 10.1063/1.3567021 10.1007/s11664-019-07412-2 10.1109/T-ED.1976.18468 10.1109/TED.2017.2669365 10.1103/PhysRevB.3.1215 |
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| Keywords | Band-2-band tunneling (B2BT) Dual source vertical tunnel FET (DSV-TFET) Low power (LP) Subthreshold slope (SS) Work function (WF) Average subthreshold slope (AVSS) |
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| Title | Design and Analysis of Dual Source Vertical Tunnel Field Effect Transistor for High Performance |
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