Solutions Strategies for Die Shift Problem in Wafer Level Compression Molding

• Published in: IEEE transactions on components, packaging, and manufacturing technology (2011) Vol. 1; no. 4; pp. 502 - 509
• Main Authors: Sharma, G, Kumar, A, Rao, V S, Soon Wee Ho, Kripesh, V
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.04.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Compounds; Copper; Design. Technologies. Operation analysis. Testing; Die shift; Electronics; embedded wafer level package; Exact sciences and technology; Fabrication; Integrated circuits; Lithography; Packaging; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Silicon; wafer molding; wafer molding; Thermal expansion; Die; Wafer-level packaging; Electronic packaging; Shrinkage; Die shift; Wafer; embedded wafer level package
• ISSN: 2156-3950; 2156-3985
• DOI: 10.1109/TCPMT.2010.2100431

Die shift problem that arises during the wafer molding process in embedded micro wafer level package fabrication was systematically analyzed and solution strategies were developed. A methodology to measure die shift was developed and applied to create maps of die shift on an 8 inch wafer. A total of 256 dies were embedded in an 8 inch mold compound wafer using compression molding. Thermal and cure shrinkages of mold compound are determined to be the primary reasons for die shift in wafer molding. Die shift value increases as the distance from the center of the wafer increases. Pre-compensation of die shift during pick and place is demonstrated as an effective method to control die shift. Applying pre-compensation method 99% of dies can be achieved to have die shift values of less than 40 μm. Usage of carrier wafer during wafer molding reduces the maximum die shift in a wafer from 633 μm to 79 μm. Die area/package area ratio has a strong influence on the die shift values. Die area/package area ratios of 0.81, 0.49, and 0.25 lead to maximum die shift values of 26, 76, and 97 μ.m, respectively. Wafer molding using low coefficient of thermal expansion (7 × 10 -6 /°C) and low cure shrinkage (0.094%) mold compounds is demonstrated to yield maximum die shift value of 28 μm over the whole 8 inch wafer area.